PCF8533 Datasheet, PDF (19/36 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates

Philips Semiconductors
Universal LCD driver for low multiplex rates
Product specification
PCF8533
7.7 I²C-bus protocol
Two I²C-bus slave addresses (01110000 and 01110010)
are reserved for the PCF8533. The least significant bit of
the slave address that a PCF8533 will respond to is
defined by the level tied at its input SA0. The PCF8533 is
a write only device and will not respond to a read access.
Therefore, two types of PCF8533 can be distinguished on
the same I²C-bus which allows:
1. Up to 16 PCF8533s on the same I²C-bus for very large
LCD applications
2. The use of two types of LCD multiplex on the same
I²C-bus.
The I²C-bus protocol is shown in Fig.14. The sequence is
initiated with a START condition (S) from the I²C-bus
master which is followed by one of the two PCF8533 slave
addresses available. All PCF8533s with the corresponding
SA0 level acknowledge in parallel to the slave address, but
all PCF8533s with the alternative SA0 level ignore the
whole I²C-bus transfer.
After acknowledgement, a control byte follows which
defines if the next byte is RAM or command information.
The control byte also defines if the next following byte is a
control byte or further RAM/command data.
In this way it is possible to configure the device then fill the
display RAM with little overhead.
The command bytes and control bytes are also
acknowledged by all addressed PCF8533s connected to
the bus.
The display bytes are stored in the display RAM at the
address specified by the data pointer and the subaddress
counter. Both data pointer and subaddress counter are
automatically updated and the data is directed to the
intended PCF8533 device.
The acknowledgement after each byte is made only by the
(A0, A1 and A2) addressed PCF8533. After the last
display byte, the I²C-bus master issues a STOP
condition (P). Alternatively a START may be issued to
RESTART an I²C-bus access.
7.8 Command decoder
The command decoder identifies command bytes that
arrive on the I²C-bus. The five commands available to the
PCF8533 are defined in Table 5.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBA607
Fig.10 Bit transfer.
1999 Jul 30
19