LPC2101_15 Datasheet, PDF(19/37 Page) NXP Semiconductors – Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC

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LPC2101_15 Datasheet, PDF (19/37 Pages) NXP Semiconductors – Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC

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NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

6.17.4 Code security (Code Read Protection - CRP)

This feature of the LPC2101/02/03 allows user to enable different levels of security in the

system so that access to the on-chip ï¬ash and use of the JTAG and ISP can be restricted.

When needed, CRP is invoked by programming a speciï¬c pattern into a dedicated ï¬ash

location. IAP commands are not affected by the CRP.

Implemented in bootloader code version 2.21 are three levels of the Code Read

Protection:

1. CRP1 disables access to chip via the JTAG and allows partial ï¬ash update (excluding

ï¬ash sector 0) using a limited set of the ISP commands. This mode is useful when

CRP is required and ï¬ash ï¬eld updates are needed but all sectors cannot be erased.

2. CRP2 disables access to chip via the JTAG and only allows full ï¬ash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to chip via

the JTAG pins and the ISP. This mode effectively disables ISP override using P0.14

pin, too. It is up to the userâs application to provide (if needed) ï¬ash update

mechanism using IAP calls or call reinvoke ISP command to enable ï¬ash update via

UART0.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Remark: Parts LPC2101/02/03 Revision â-â have CRP2 enabled only (bootloader code

version 2.2).

6.17.5 External interrupt inputs

The LPC2101/02/03 include up to three edge or level sensitive external interrupt inputs as

selectable pin functions. When the pins are combined, external events can be processed

as three independent interrupt signals. The external interrupt inputs can optionally be

used to wake-up the processor from Power-down mode and Deep power-down mode.

Additionally all 10 capture input pins can also be used as external interrupts without the

option to wake the device up from Power-down mode.

6.17.6 Memory mapping control

The memory mapping control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ï¬ash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

6.17.7 Power control

The LPC2101/02/03 supports three reduced power modes: Idle mode, Power-down

mode, and Deep power-down mode.

LPC2101_02_03_4

Product data sheet

Rev. 04 â 2 June 2009

19 of 37

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