TDA1373H Datasheet, PDF (18/40 Pages) NXP Semiconductors – General Digital Input GDIN

Philips Semiconductors
General Digital Input (GDIN)
Product specification
TDA1373H
IN-BAND NOISE SHAPING (INS)
The standard 20-bit output word length can be reduced to
16 or 18 bits to match digital consumer equipment.
Normally 16 bit output re-quantization at audio-band
sample rates drops the signal-to-noise ratio (S/N)
inevitably to 95 dB, because of the re-quantization noise at
−98 dB.
It is possible however to shape the re-quantization noise in
a psycho-acoustical way. This reduces the re-quantization
noise at the frequencies where the human ear is most
sensitive and stores the bulk of re-quantization noise at
high frequencies, where the human ear is quite insensitive.
The In-band Noise Shaping function (to 16 or 18 bits)
results in a subjective quality improvement of about 2 bits
below the actual quantization level.
It is also possible to re-quantize the 20 bit output to 16 bits
without noise shaping but by a simple rounding operation.
Table 5 gives an overview of the 4 possible settings.
Table 5 Selectable output word lengths
QU1
0
0
1
1
QU0
0
1
0
1
WORD LENGTH
16 bit (rounded)
20 bit
16 bit INS⁽¹⁾
18 bit INS⁽¹⁾
Note
1. INS = In-band Noise Shaping.
BITSTREAM DIGITAL FILTER
The Bitstream digital filter generates a Bitstream signal
which should be filtered by a Bitstream DAC
(e.g. TDA1547) to become a high-quality analog signal.
The input for this block can be selected from the output of
the up-sample path or directly from serial input DI2. In this
case, the input signal applied to DI2 should be externally
oversampled to 4f_so and further oversampling will be
carried out by the hold function. The Bitstream signal has
a frequency of 128f_so (SRC and SLAVE modes) or 192f_so
(AD/DA mode).
To prevent idle patterns in the audio band, it is strongly
advised to add out-of-band dither by setting
control bit NSD.
DIGITAL PLL
The digital PLL controls the variable hold function which
steers the actual SRC process. An adaptive loop filter
allows fast locking to the input frequency and a small
bandwidth during steady-state. At start-up, the bandwidth
of the 3-step digital loop filter is gradually reduced to
0.5 Hz. A difference frequency of 1 Hz is reached within
512 input samples (10 ms at 44.1 kHz), which allows to
start the SRC. At this moment the outputs are de-muted,
indicated at pin MU and status flag MUT.
The FIFO position is continuously monitored to control the
adaptive loop filter. The loop filter switches back to a fast
state when the FIFO tends to drift, e.g. during pitch control
on the input signal. It is possible to fix the loop filter in one
of the three states. In the adaptive mode, the actual state
can be monitored by the microcontroller (ST1 and ST0). In
SRC mode, the microcontroller can retrieve the exact input
sample frequency via the status registers STS3 and STS4.
Table 6 PLL operation modes
LC1
LC0
PLL
OPERATION
PLL BANDWIDTH
(Hz)
0
0 adaptive
500, 50 or 0.5
0
1 state 1 fixed 500
1
0 state 2 fixed 50
1
1 state 3 fixed 0.5
In both SLAVE modes, a pulse modulated signal at
pin FSL is present to control the external VC(X)O. In
SLAVE-VCO mode, CLI is the clock input of the GDIN and
in SLAVE-VCXO mode XTLI is the clock input. An external
1000 Hz low-pass filter retrieves the control voltage for the
VC(X)O. To get the loop characteristics as described
above, the centre frequency of the VCO should be at
1_{⁄2VDD and the sensitivity should be:}
g_v = ^{7----6--12---8--V--f--s}-_D-^o--_D--⁽--^c--⁾- Hz/V.
The maximum VCO frequency range is:
(768 × 0.3)f_so(c) < 768f_si (=f_so) < (768 × 1.7)f_so(c) (49 kHz).
IEC 958 CHANNEL STATUS AND USER CHANNEL EXTRACTOR
(CUP)
The internal ADIC retrieves also the Channel Status (CS)
and User Channel (UC) bits from the IEC 958 signal. The
C/U processing function block can be programmed for
4 different functions (see Table 7).
1996 Jul 17
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