PBSS4112PANP_15 Datasheet, PDF (18/21 Pages) NXP Semiconductors – 120 V, 1 A NPN/PNP low VCEsat (BISS) transistor

NXP Semiconductors
PBSS4112PANP
120 V, 1 A NPN/PNP low VCEsat (BISS) transistor
9. Package outline
2.1
1.9
1.1
0.9
0.77
0.57 3
(2×)
2.1
1.9 ^0.54
0.44
(2×) 1
0.3
0.2
Dimensions in mm
Fig. 30. Package outline DFN2020-6 (SOT1118)
4 _0.65
(4×)
0.35
6 0.25
(6×)
0.65
max
0.04
max
10-05-31
10. Soldering
2.1
0.65
0.65
0.49
0.49
0.875
2.25
0.875
0.3 0.4
(6×) (6×)
1.05 1.15
(2×) (2×)
0.35
0.72
(6×)
(2×)
0.45
0.82
(6×)
(2×)
Fig. 31. Reflow soldering footprint for DFN2020-6 (SOT1118)
solder lands
solder paste
solder resist
occupied area
Dimensions in mm
sot1118_fr
11. Revision history
Table 8. Revision history
Data sheet ID
Release date
PBSS4112PANP v.1 20121129
Data sheet status
Product data sheet
Change notice
-
PBSS4112PANP
Product data sheet
All information provided in this document is subject to legal disclaimers.
29 November 2012
Supersedes
-
© NXP B.V. 2012. All rights reserved
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