AN10658_15 Datasheet, PDF (18/28 Pages) NXP Semiconductors – Sending I2C-bus signals via long communications cables

NXP Semiconductors
AN10658
Sending I²C-bus signals via long communications cables
4.4.1 Example 1: Timings measured driving 50 m of cable between two P82B96s
in 4-wire mode
Blue Magenta Yellow
Green
Blue trace: SCL generated by the Master and applied at Sx of the P82B96 at the ‘send’ end of the
cable.
Magenta trace: SCL signal as received at the PCA9633 slave at the remote end of the cable.
Green trace: SDA signal at the PCA9633 pin, at the remote end of the cable.
Yellow trace: SDA signal from PCA9633 as received from Sx back at the pin of the Master.
Fig 13. Driving PCA9633 at 350 kHz via a 50 m cable using P82B96 and 4-signal mode
Some of the important timing components are illustrated in Figure 13.
Firstly, the Master SCL signal as received by the PCA9633 slave has been delayed by
about 620 ns by the cable and the two P82B96 buffers. The contributions (not shown
here) are:
• the time for SCL to fall from 2.5 V (nominal logic threshold for the Master) to the
0.65 V switching threshold of Sx, about 50 ns
• propagation through P82B96 Sx to Tx at the Master end, including Tx fall time is 70 ns
• the cable propagation delay of approximately 5 ns/m or 250 ns
• the propagation from Rx to Sx at the slave end is 250 ns.
Total delay is 620 ns.
Next, the PCA9633 SDA provides an acknowledge of the received byte as shown by the
green trace falling from the 0.8 V level output set by Sx to the near 0 V low driven by the
PCA9633. The delay time to acknowledge is 200 ns. That represents the t_VD;ACK delay or
time to produce a valid ACK following the falling edge of the SCL that requests it.
AN10658_1
Application note
Rev. 01 — 26 February 2008
© NXP B.V. 2008. All rights reserved.
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