TDA4680 Datasheet, PDF (17/28 Pages) NXP Semiconductors – Video processor with automatic cut-off and white level control

Philips Semiconductors
Video processor with automatic cut-off
and white level control
Product specification
TDA4680
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
I²C-bus transceiver clock SCL (pin 28)
f_SCL
input frequency range
V_IL
LOW level input voltage
V_IH
HIGH level input voltage
I_IL
LOW level input current
I_IH
HIGH level input current
t_L
clock pulse LOW
t_H
clock pulse HIGH
t_r
rise time
t_f
fall time
V₂₈ = 0.4 V
0
−
−
−
3.0 −
−10 −
−
−
4.7 −
4.0 −
−
−
−
−
100
kHz
1.5
V
6.0
V
−
µA
10
µA
−
µs
−
µs
1.0
µs
0.3
µs
I²C-bus transceiver data input/output SDA (pin 27)
V_IL
V_IH
I_IL
I_IH
I_OL
t_r
t_f
t_SU;DAT
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
LOW level output current
rise time
fall time
data set-up time
V₂₇ = 0.4 V
V₂₇ = 0.4 V
−
−
3.0 −
−10 −
−
−
3.0 −
−
−
−
−
0.25 −
1.5
V
6.0
V
−
µA
10
µA
−
mA
1.0
µs
0.3
µs
−
µs
Notes to the characteristics
1. The values of the −(B − Y) and −(R − Y) colour difference input signals are for a 75% colour-bar signal.
2. The pins are capacitively coupled to a low ohmic source, with a recommended maximum output impedance of 600 Ω.
3. The white potentiometers affect the amplitudes of the RGB output signals including the white measurement pulses.
4. The RGB outputs at pins 24, 22 and 20 are emitter followers with current sources.
5. Sandcastle pulses are compared with internal threshold voltages independent of V_P. The threshold voltages
separate the components of the sandcastle pulse. The particular component is generated when the voltage on pin 14
exceeds the defined internal threshold voltage.
The internal threshold voltages (control bit SC5 = 0) are:
1.5 V for horizontal and vertical blanking pulses
3.5 V for horizontal pulses
6.0 V for the burst key pulse.
The internal threshold voltages (control bit SC5 = 1) are:
1.5 V for horizontal and vertical blanking pulses
3.5 V for the burst key pulse.
6. A sandcastle pulse with a maximum voltage equal to (V_P + 0.7 V) is obtained by limiting a 12 V sandcastle pulse.
7. Average beam current limiting reduces the contrast, at minimum contrast it reduces the brightness.
8. Peak drive limiting reduces the RGB outputs by reducing the contrast, at minimum contrast it reduces the brightness.
The maximum RGB outputs are determined via the I²C-bus under sub-address 0AH. When an RGB output exceeds
the maximum voltage, peak drive limiting is delayed by one horizontal line.
1996 Oct 25
17