PCF2103 Datasheet, PDF(17/56 Page) NXP Semiconductors

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PCF2103 Datasheet, PDF (17/56 Pages) NXP Semiconductors – LCD controllers/drivers

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Philips Semiconductors

LCD controllers/drivers

Product speciï¬cation

PCF2103 family

8 INSTRUCTIONS

Only two PCF2103 registers, the Instruction Register (IR)

and the Data Register (DR) can be directly controlled by

the microcontroller. Before internal operation, control

information is stored temporarily in these registers to allow

interface to various types of microcontrollers which

operate at different speeds or to allow interface to

peripheral control ICs. The format for instructions when

I2C-bus control is used is shown in Table 6. The PCF2103

operation is controlled by the instructions given in Table 7

together with their execution time. Details are explained in

subsequent sections.

Instructions are of 4 types, those that:

1. Designate PCF2103 functions such as display format,

data length, etc.

2. Set internal RAM addresses

3. Perform data transfer with internal RAM

4. Others.

In normal use, instructions that perform data transfer with

internal RAM are used most frequently. However,

automatic incrementing by 1 (or decrementing by 1) of

internal RAM addresses after each data write lessens the

microcontroller program load. The display shift in particular

can be performed concurrently with display data write,

enabling the designer to develop systems in minimum time

with maximum programming efficiency.

During internal operation, no instruction other than the

âread busy flag and address counterâ instruction will be

executed. Because the busy flag is set to logic 1 while an

instruction is being executed, the user should verify that

the busy flag is at logic 0 before sending the next

instruction or wait for the maximum instruction execution

time, as given in Table 7. An instruction sent while the

busy flag is logic 1 will not be executed.

Table 6 Instruction set for I2C-bus commands

CONTROL BYTE

COMMAND BYTE

I2C-BUS COMMANDS

Co RS 0 0 0 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 note 1

Note

1. R/W is set together with the slave address.

1998 May 11

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