74AVCH2T45_15 Datasheet, PDF (17/27 Pages) NXP Semiconductors – Dual-bit, dual-supply voltage level translator/transceiver; 3-state

NXP Semiconductors
74AVCH2T45
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
13.3 Power-up considerations
The device is designed such that no special power-up sequence is required other than
GND being applied first.
Table 18.
V_CC(A)
Typical total supply current (I_CC(A) + I_CC(B))
V_CC(B)
0V
0.8 V 1.2 V 1.5 V 1.8 V
0V
0
0.1
0.1
0.1
0.1
0.8 V 0.1
0.1
0.1
0.1
0.1
1.2 V 0.1
0.1
0.1
0.1
0.1
1.5 V 0.1
0.1
0.1
0.1
0.1
1.8 V 0.1
0.1
0.1
0.1
0.1
2.5 V 0.1
0.7
0.3
0.1
0.1
3.3 V 0.1
2.3
1.4
0.9
0.5
2.5 V
0.1
0.7
0.3
0.1
0.1
0.1
0.1
3.3 V
0.1
2.3
1.4
0.9
0.5
0.1
0.1
Unit
A
A
A
A
A
A
A
13.4 Enable times
The enable times for the 74AVCH2T45 are calculated from the following formulas:
• t_en (DIR to nA) = t_dis (DIR to nB) + t_pd (nB to nA)
• t_en (DIR to nB) = t_dis (DIR to nA) + t_pd (nA to nB)
In a bidirectional application, these enable times provide the maximum delay from the
time the DIR bit is switched until an output is expected. For example, if the 74AVCH2T45
initially is transmitting from A to B, then the DIR bit is switched, the B port of the device
must be disabled before presenting it with an input. After the B port has been disabled, an
input signal applied to it appears on the corresponding A port after the specified
propagation delay.
74AVCH2T45
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 2 April 2013
© NXP B.V. 2013. All rights reserved.
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