TDA2579C Datasheet, PDF (15/24 Pages) NXP Semiconductors – Synchronization circuit with synchronized vertical divider system for 60 Hz

Philips Semiconductors
Synchronization circuit with synchronized
vertical divider system for 60 Hz
Preliminary specification
TDA2579C
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Internal vertical sync pulse separator
t_d1
delay between video signal at pin 5 and
internally separated vertical sync pulse;
normal signal condition
t_d2
delay between video signal at pin 5 and
internally separated vertical sync pulse;
noisy signal condition
V₁₈ ≥ 1.2 V
12
19
25
µs
−
−
−17 µs
Notes to the characteristics
1. Value inclusive R_L pin 11 to pin 16 = 6.8 kΩ.
2. Up to 1 V peak-to-peak the slicing level is constant, at amplitudes exceeding 1 V peak-to-peak the slicing level will
increase.
3. The slicing level is fixed by the formula:
p = -5---.-3---R--_×--^s---R-----_s × 100%.
Where R_S is the resistor between pins 6 and in kΩ; top sync = 100%.
4. S/N = 20 log ^{V----i--d---e---o-----v---o----l-t--a---g-N--e---o--(-i-bs---e-l-a---c(--R-k----M--t--o-S-----w)----h----i-t--e-----s---i-g---n---a----l-)-}
A low-pass filter of 1 kΩ and 150 pF decreases the noise content of the CVBS signal by 6 dB.
5. Undercompensated.
6. Overcompensated.
7. Measured between pin 5 and sandcastle output pin 17.
8. Measured with 3.3 µF feedback capacitor between pin 16 and 6.8 µF capacitor in PLL filter pin 8.
9. Maximum divider ratio (60 Hz):
n = ^2-----×_f--V---f--^H-- = 576 (2 clock pulses per video line).
Start vertical blanking:
− search (large) window mode (60 Hz)
− reset divider = start vertical sync pulse plus 1 clock pulse
− small/standard window mode (60 Hz)
− clock pulse 517.
Stop vertical blanking:
− all window modes (60 Hz)
− clock pulse 34.
10. Depends on DC level of pin 5, value given is valid for V₅ ≈ 5 V.
11. Valid for ^2-----×_f--V---f--^H-- < 576.
12. Value related to internal Zener diode reference voltage. Spread includes complete spread of reference voltage.
January 1994
15