SC16C652B Datasheet, PDF (15/44 Pages) NXP Semiconductors – 5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder

Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7. Register descriptions
Table 9 details the assigned bit functions for the SC16C652B internal registers. The
assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
Table 9: SC16C652B internal registers
Shaded bits are only accessible when EFR[4] is set.
A2 A1 A0 Register Default^[1] Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1
Bit 0
General Register Set^[2]
0 0 0 RHR XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0 0 0 THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0 0 1 IER
00
CTS
RTS
Xoff
Sleep
interrupt interrupt interrupt mode
modem
status
interrupt
Rx
receive
line
status
interrupt
transmit
holding
register
interrupt
receive
holding
register
0 1 0 FCR
00
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
TX
trigger
(MSB)
TX
trigger
(LSB)
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFOs
enable
0 1 0 ISR
01
FIFOs
enabled
FIFOs
enabled
INT
priority
bit 4
INT
priority
bit 3
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0 1 1 LCR
00
divisor
latch
enable
set break set parity even
parity
parity
enable
stop bits word
length
bit 1
word
length
bit 0
1 0 0 MCR 00
clock
select
IRDA 0
enable
loop back OP2/INT (OP1) RTS
enable
DTR
1 0 1 LSR
60
FIFO
data
error
THR and THR
TSR
empty
empty
break framing parity
interrupt error error
overrun
error
receive
data
ready
1 1 0 MSR X0
CD
RI
DSR
CTS
∆CD
∆RI
∆DSR ∆CTS
1 1 1 SPR
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Special Register Set^[3]
0 0 0 DLL
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0 0 1 DLM
XX
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Enhanced Register Set^[4]
0 1 0 EFR
00
Auto
CTS
Auto
RTS
Special
char.
select
Enable Cont-3
IER[4:7], Tx, Rx
ISR[4:5], Control
FCR[4:5],
MCR[5:7]
Cont-2
Tx, Rx
Control
Cont-1
Tx, Rx
Control
Cont-0
Tx, Rx
Control
1 0 0 Xon-1 00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1 0 1 Xon-2 00
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
1 1 0 Xoff-1 00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1 1 1 Xoff-2 00
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
[1] The value shown in represents the register’s initialized HEX value; X = n/a.
[2] Accessible only when LCR[7] is logic 0.
[3] Baud rate registers accessible only when LCR[7] is logic 1.
[4] Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF_Hex’.
9397 750 14452
Product data
Rev. 03 — 10 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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