SAA6750H Datasheet, PDF (15/60 Pages) NXP Semiconductors – Encoder for MPEG2 image recording EMPIRE

Philips Semiconductors
Encoder for MPEG2 image recording
(EMPIRE)
Product specification
SAA6750H
7.2.3 DESCRIPTION OF OPERATING MODES
Depending on the reset processing and the setting of the
I²C-bus control bits E_ST and E_SP (see Tables 22
and 23) the SAA6750H can be set to different operating
modes. Purpose and behaviour are described in Table 1.
After an external reset pulse at RESETN, the init mode will
be active because control bits E_ST and E_SP are set to
LOW.
7.2.4 PIN BEHAVIOUR
The behaviour of I/O and output pins is depending on the
operation mode of the SAA6750H. In reset mode the pins
are forced to a certain behaviour even if no clock VCLK is
available. Reset mode overrules all other internal pin
settings. During soft reset mode all output and I/O pins that
could create driver conflicts with other devices are forced
to 3-state or input mode. The internal reset is active during
a period of 7562 clock cycles after reset mode and soft
reset mode. The status of pins is determined by the reset
behaviour of the internal modules. The internal reset
behaviour applies also for the init mode because init mode
always follows internal reset.
In operation mode the status of the pins is depending on
the function of the SAA6750H.
Table 1 SAA6750H operating modes
MODE
ACTIVATED BY
RESETN E_ST E_SP
DESCRIPTION
Reset mode
Init mode
0
X
X In reset mode all I/O and output pins are forced to a defined state with
RESETN = LOW (refer to Table 2). After VCLK is available, also the
internal reset becomes active, which puts the internal modules in reset
state. The I²C-bus control register is cleared in this mode. After setting
RESETN back to HIGH, the internal reset will remain active for 7562
clock cycles. The DRAM initialization sequence will run during this time
(see Section 7.10.3.2).
1
0
0 In init mode the device initialization via the I²C-bus has to be performed.
The external DRAM is not refreshed. See Table 2 for behaviour of pins
during init mode. This mode will be active after external reset due to reset
of E_ST and E_SP.
Remark: Do not switch from operating mode to init mode directly. Always
use the soft reset or reset mode as intermediate step.
Soft reset mode
1
0
1 Activates the internal synchronous reset. All internal modules except the
I²C-bus control register are in reset mode. This mode allows e.g.
operation of a second device SAA6750H. Therefore output and I/O pins
are in input or 3-state mode (see Table 2). The external DRAM will not be
refreshed. After setting E_SP back to LOW, the internal reset will remain
active for 7562 clock cycles. The DRAM initialization sequence will run
during this time (see Section 7.10.3.2).
Operating mode
1
1
0 Normal operating.
−
1
1
1 Internal use only.
2000 May 03
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