PTN3381DBS Datasheet, PDF (15/30 Pages) NXP Semiconductors – Enhanced performance HDMI/DVI level shifter with voltage regulator, dongle detection and supporting 3 Gbit/s operation

NXP Semiconductors
PTN3381D
Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation
7.7 Characteristics of the I²C-bus
The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.7.1 Bit transfer
One data bit is transferred during each clock phase. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at this
time will be interpreted as control signals (see Figure 5).
SDA
SCL
Fig 5. Bit transfer
data line
stable;
data valid
change
of data
allowed
mba607
7.7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P). See Figure 6.
SDA
SCL
S
START condition
Fig 6. Definition of START and STOP conditions.
P
STOP condition
mba608
7.7.3 System configuration
An I²C-bus device generating a message is a ‘transmitter’, a device receiving is the
‘receiver’. The device that controls the message is the ‘master’ and the devices which are
controlled by the master are the ‘slaves’. See Figure 7.
PTN3381D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 July 2012
© NXP B.V. 2012. All rights reserved.
15 of 30