PCD5096 Datasheet, PDF (15/52 Pages) NXP Semiconductors – Universal codec

Philips Semiconductors
Universal codec
Preliminary specification
PCD5096
8.3.4 CONTROL REGISTER 2 (CR2)
CR2 contains the gain setting values of the analog Codec 1 and Codec 2 section. The state of CR2 after reset is 0000H.
This sets the A/D path and the D/A path gain to their minimum values of +9 dB and −13 dB respectively.
The D/A path gain is defined as the relationship between the level of the analog output signal, differentially seen at
EARP_HS - EARM_HS or LIFP_DA1 - LIFM_DA1, expressed in dBm (0 dBm0 is 1 mW in 600 Ω), and the level of the
digital input signal at the PCM interface, expressed in dBm0 according to CCITT Recommendation G.711. This D/A path
gain definition assumes that the volume control in the DSP is set to the default value of 0 dB.
The A/D path gain is defined as the relationship between the level of the digital output signal at the PCM interface,
expressed in dBm0, and the level of the analog input signal at the LIF interface, differentially seen at
LIFP_AD2 - LIFM_AD2 or LIFP_AD1 - LIFM_AD1, expressed in dBm.
Table 11 Control Register 2 (address 7AH)
15
DA2.3
14
DA2.2
13
DA2.1
12
DA2.0
11
AD2.3
10
AD2.2
9
AD2.1
8
AD2.0
Table 12 Control Register 2 (continued)
7
DA1.3
6
DA1.2
5
DA1.1
4
DA1.0
3
AD1.3
2
AD1.2
1
AD1.1
0
AD1.0
Table 13 Description of CR2 bits
BIT
SYMBOL
DESCRIPTION
15
DA2.3 These 4 bits select the D/A path gain for Codec 2; see Table 14.
14
DA2.2
13
DA2.1
12
DA2.0
11
AD2.3 These 4 bits select the A/D path gain for Codec 2; see Table 15.
10
AD2.2
9
AD2.1
8
AD2.0
7
DA1.3 These 4 bits select the D/A path gain for Codec 1; see Table 14.
6
DA1.2
5
DA1.1
4
DA1.0
3
AD1.3 These 4 bits select the A/D path gain for Codec 1; see Table 15.
2
AD1.2
1
AD1.1
0
AD1.0
1997 Jan 22
15