LPC1759_15 Datasheet, PDF (15/80 Pages) NXP Semiconductors – 32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN

NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
8.5 Memory Protection Unit (MPU)
The LPC1759/58/56/54/52/51 have a Memory Protection Unit (MPU) which can be used
to improve the reliability of an embedded system by protecting critical data within the user
application.
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to 8 regions each of which can be
divided into 8 subregions. Accesses to memory locations that are not defined in the MPU
regions, or not permitted by the region setting, will cause the Memory Management Fault
exception to take place.
8.6 Memory map
The LPC1759/58/56/54/52/51 incorporate several distinct memory regions, shown in the
following figures. Figure 3 shows the overall map of the entire address space from the
user program viewpoint following reset. The interrupt vector area supports address
remapping.
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
LPC1759_58_56_54_52_51
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8.6 — 18 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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