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TSA5522 Datasheet, PDF (14/20 Pages) NXP Semiconductors – 1.4 GHz I2C-bus controlled synthesizer | |||
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Philips Semiconductors
1.4 GHz I2C-bus controlled synthesizer
Product speciï¬cation
TSA5522
Flock ï¬ag (FL) deï¬nition
When the LOCK output is LOW the maximum frequency
deviation (âf) from stable frequency can be expressed as
follows: âf = ±-K---K-V---CO----O-- à ICP à --((--CC-----11-----+Ã----CC-----22----))-
where:
Kvco = oscillator slope Hz/V
ICP = charge-pump current (A)
KO = 4 Ã 10E6
C1, C2 = loop filter capacitors.
In the application:
KVCO = 16 MHz/V (UHF band)
ICP = 250 µA
C1 = 180 nF, C2 = 39 nF
âf = ±31.2 kHz.
handbook, halfpage
C2
C1
R
MBE331
Fig.7 Loop filter.
Table 9 LOCK output / FL ï¬ag setting
DESCRIPTION
CONDITION
Time span between actual phase lock and LOCK bit is LOW RSA = 1; RSB = 1
(or FL ï¬ag = 1)
RSA = 1; RSB = 1
RSB = 0
Time span between the loop losing lock and LOCK bit is
HIGH or (FL ï¬ag = 0)
MIN.
1 024
2 048
1 280
0
MAX.
1 152
2 304
1 440
300
UNIT
µs
µs
µs
µs
1996 Jan 23
14
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