TDA5341 Datasheet, PDF (14/28 Pages) NXP Semiconductors – Brushless DC motor and VCM drive circuit with speed control

Philips Semiconductors
Brushless DC motor and VCM drive circuit
with speed control
Product specification
TDA5341
Speed control function
Speed control is efficiently achieved by the
frequency-locked loop circuitry which is enabled by bit D20
of the CONTROL register.
Its aim is to keep the tachometer signal set to a reference
programmed by the user via the serial port (see Section
“Serial port”).
The FLL operates as follows:
When power is first applied to the circuit, the FILTER pin is
pulled HIGH so that maximum output current can be
sourced for optimum torque.
FG pulses will appear rapidly so as to provide a ‘clean’
clock signal (FMOT) that will issue one pulse per
mechanical revolution. This may be used for speed
regulation, by re-entering the signal through the DPULSE
pin. Then, after it has been synchronised to the ROSC
clock, it is compared to an accurate reference derived from
the ROSC clock and programmed by the user via the serial
port. The resulting variation in frequency generates a
speed error term that will switch a charge-pump up or
down in order to charge or discharge an external RC filter
(FILTER). The voltage at the FILTER pin is then used as
an input to the current control amplifier that regulates the
current in both upper and lower NMOS transistors.
A velocity regulation based upon (maximum) one
corrective action per mechanical revolution may be
considered insufficient in some applications. That is the
reason why the second input of the FLL circuitry was
intentionally left open-circuit and directly accessible to the
external world via pin DPULSE. In that way, total freedom
is given to the user to use any signal coming out of the
microcontroller in order to regulate the motor velocity with
a finer accuracy.
Moreover, a mixed regulation is also possible: firstly,
the FMOT signal is fed via DPULSE into the FLL circuitry
and then once data is read out off the disc, it is switched to
another clock signal with a higher frequency than FMOT.
Simultaneously, a new division factor is programmed via
the serial port.
It should be noted that there is no need for external
synchronization. However, it is recommended to change
the division factor and the DPULSE clock rate during the
period when FMOT is HIGH.
Serial port
The serial port operates as follows:
When ENABLE is HIGH, the serial port is disabled, which
means the TDA5341 functions regardless of any change
at pins DATA and CLOCK.
When ENABLE is set LOW some set-up time before the
falling edge of CLOCK, the serial port is enabled, i. e. data
is serially shifted into the 24-bit shift register on the falling
edge of the CLOCK signal. The least significant bit
(LSB = DATA 0) is the first in, DATA(23) the MSB is the
last in.
When ENABLE goes HIGH, the contents of the shift
register are loaded into the internal fixed register
(CONTROL register), it will not change until the next rising
edge of ENABLE.
It should be noted that when RESET goes HIGH it will
force all bits of the shift register and the control register to
logic 0. However, there is no reset effect on both power-up
and power-down i.e there is no correlation between
RESET and RESETOUT.
CLOCK can be stopped (either in the HIGH or LOW state)
once RESET or ENABLE have been asserted.
The 24-bit control register is organized as follows:
• D23: SPINDLE DISABLE
– When LOW, the spindle circuitry is enabled
• D22: VCM DISABLE
– When LOW, the actuator circuitry is enabled
• D21: PARK
– When HIGH, it enables the head retraction. This has
the same effect as pin RETRACT pulled LOW
• D20: FLL ENABLE
– When HIGH, it closes the complete speed regulation
loop
– When LOW, it will set the output of the charge pump
(FILTER) to the high impedance state
• D19 and D18
– The combination of these bits fixes the division factor
to apply on the FG signal with respect to the number
of poles.
1997 Jul 10
14