SZA1000 Datasheet, PDF (14/32 Pages) NXP Semiconductors – QIC digital equalizer

Philips Semiconductors
QIC digital equalizer
Product specification
SZA1000
Address 27: Amplitude detector slope qualification delay
Table 10 Qualification delay: QUAL_SLOPE_DEL; notes 1 and 2
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
DEL.1
DEL.0
SL.1
SL.0
Notes
1. DEL is the programmable compensation delay, in cycles of f_s, between the qualifier and the analog zero crossing of
the read pulse circuit; DEL is a 2-bit unsigned value
2. SL selects the decay time of the amplitude detectors.
Table 11 Amplitude detector decay time ^5---f-0-_s--0--
SL
DECAY TIME
0
-5--f-0-_s--0--
1
1----0-f--_s0----0-
2
2----0-f--_s0----0-
3
4----0-f--_s0----0-
Table 12 Variable qualifier threshold
GP, GN
0
1
2
3
4, 5, 6, 7
VARIABLE THRESHOLD
0
1_⁄8
1_⁄4
3_⁄8
1_⁄2
GAP DETECTOR FUNCTIONS
Address 28: Fixed threshold: GAP_THRESH
Fixed threshold for the gap detector; 8-bit signed value.
WRITE EQUALIZATION (WEQ) FUNCTIONS
Address 29: WEQ settings
Table 13 Time slots: WEQ_SET0; see Table 14
D7
D6
D5
D4
−
−
−
−
Table 14 Time slots in channel bit cell
NUMBER OF TIME SLOTS
N6
2
0
3
0
6
1
D3
D2
−
N6
N3
0
1
0
D1
D0
N3
N2
N2
1
0
0
1998 Feb 16
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