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SAA2032 Datasheet, PDF (14/28 Pages) NXP Semiconductors – Digital equalization for the tape drive processing of the DCC system
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Philips Semiconductors
Digital equalization for the tape
drive processing of the DCC system
Product specification
SAA2032
LTENDEQ
LTCNT0/1
LTCLK
LTDATA
bit
t Le
t su1
t h1
t su4
t su2
t Lc
tHc
tsu3
t h3
0
1
t h2
MCD485 - 1
tLe > 120 ns; minimum LOW time LTENDEQ before transfer.
tsu1 > 20 ns; set-up time LTCNT0/1 before LTENDEQ HIGH.
th1 > 100 ns; hold time LTCNT0/1 after LTENDEQ HIGH.
tsu2 ≥ 0 ns; set-up time LTCNT0/1 before LTCLK LOW.
th2 > 20 ns; hold time LTENDEQ after LTCLK HIGH.
tLc > 120 ns; minimum LOW time LTCLK.
tHc > 120 ns; minimum HIGH time LTCLK.
tsu4 > 200 ns; set-up time LTCLK before LTENDEQ HIGH.
tsu3 > 100 ns; set-up time LTDATA before LTCLK HIGH.
th3 > 20 ns; hold time LTDATA after LTCLK HIGH.
Fig.15 Microcontroller to SAA2032 timing.
February 1995
14
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