PCF8563 Datasheet, PDF (14/30 Pages) NXP Semiconductors – Real-time clock/calendar

Philips Semiconductors
PCF8563
Real-time clock/calendar
8.9.3 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as a control signal; see Figure 8.
dth
SDA
SCL
data line
stable;
data valid
Fig 8. Bit transfer on the I²C-bus.
change
of data
allowed
MBC621
8.9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related
clock pulse.
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte. Also a master receiver must generate an acknowledge after
the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
width
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
9397 750 04855
Product specification
SCL FROM
MASTER
1
2
S
START
condition
Fig 9. Acknowledge on the I²C-bus.
16 April 1999
not acknowledge
acknowledge
8
9
clock pulse for
acknowledgement
MBC602
© Philips Electronics N.V. 1999. All rights reserved.
14 of 30