FI1216MK2 Datasheet, PDF (14/20 Pages) NXP Semiconductors – Desktop video tuner system CCIR B/G

Philips Components
Desktop video tuner
system CCIR B/G
Preliminary specification
FI1216MK2
READ mode
The in-lock can be read by setting the R/W bit to 1.
BITS
BYTE
7
MSB
6
5
4
3
2
1
0
LSB
A⁽⁵⁾
Address byte
1
1
0
0
0
MA1
MA0
1
A
Status byte
POR⁽¹⁾
FL⁽²⁾
I2⁽³⁾
I1⁽³⁾
I0⁽³⁾
A2⁽⁴⁾
A1⁽⁴⁾
A0⁽⁴⁾
A
Notes
1. POR = Power On Reset. POR is internally set to 1 in case V_S drops below 3 V. The POR bit is reset when an end of
data is detected by the PLL IC.
2. FL = In-lock flag; FL = 1: loop is phase-locked. The loop must be phase-locked during at least 8 periods of the internal
7.8125 kHz reference frequency before the FL flag is internally set to 1.
3. I2, I1 and I0 = digital information for I/O ports P2, P1 and P0 respectively.
4. A2, A1 and A0 = built-in 5-level A/D converter on I/O port P6. AFC information to the controller of the IF section is
available on pin 10 (see Table “Digital AFC status”).
5. A = Acknowledge.
TELEGRAM EXAMPLES (READ MODE)
Start - Adb - Ack - STB - Ack - STB - - Stop (no Ack from processor = End-of-data).
Start - Adb - Ack - STB - - Stop (no Ack from processor = End-of-data).
Where:
STB = Status byte.
Video buffer
A video buffer is built into the video module to enable the
unit to drive a 75 Ω load directly. In case it is required to
use the FI1216MK2 as a replacement for the FI1216 in the
same videocard, it is necessary to replace the 75 Ω series
resistor in the video card by a 0 Ω series resistor. At the
same time the 22 kΩ series resistor in the tuning supply
must be removed.
I²C-bus load
The FI1216MK2 contains a series resistor (R = 100 Ω) in
the SCL and SDA lines. Both lines also have a capacitive
load of typical 56 pF (see Fig.3).
handbook, halfpage
VCC
R1
R2
PLL IC
R3
100 Ω
15
AS
C1
56 pF
R4
100 Ω
R5
100 Ω
C2
56 pF ₁₄
SDA
13
SCL
C3
56 pF
MBH031
1997 Mar 13
Fig.3 I²C-bus load.
14