8XC552 Datasheet, PDF (14/60 Pages) NXP Semiconductors – 80C51 FAMILY DERIVATIVES

Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
SDA
(3)
(1)
(1)
(2)
SCL
1
2
3
4
8
9
ACK
1. Another device transmits identical serial data.
2. Another device overrules a logic 1 (dotted line) transmitted by SIO1 (master) by pulling the SDA line low. Arbitration is
lost, and SIO1 enters the slave receiver mode.
3. SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. SIO1 will
not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration.
Figure 13. Arbitration Procedure
SDA
(1)
(3)
(1)
SCL
(2)
Mark
Duration
Space Duration
1. Another service pulls the SCL line low before the SIO1 “mark” duration is complete. The serial clock generator is immediately
reset and commences with the “space” duration by pulling SCL low.
2. Another device still pulls the SCL line low after SIO1 releases SCL. The serial clock generator is forced into the wait state
until the SCL line is released.
3. The SCL line is released, and the serial clock generator commences with the mark duration.
Figure 14. Serial Clock Synchronization
ARBITRATION AND SYNCHRONIZATION LOGIC
In the master transmitter mode, the arbitration logic checks that
every transmitted logic 1 actually appears as a logic 1 on the I²C
bus. If another device on the bus overrules a logic 1 and pulls the
SDA line low, arbitration is lost, and SIO1 immediately changes from
master transmitter to slave receiver. SIO1 will continue to output
clock pulses (on SCL) until transmission of the current serial byte is
complete.
Arbitration may also be lost in the master receiver mode. Loss of
arbitration in this mode can only occur while SIO1 is returning a “not
acknowledge: (logic 1) to the bus. Arbitration is lost when another
device on the bus pulls this signal LOW. Since this can occur only at
the end of a serial byte, SIO1 generates no further clock pulses.
Figure 13 shows the arbitration procedure.
The synchronization logic will synchronize the serial clock generator
with the clock pulses on the SCL line from another device. If two or
more master devices generate clock pulses, the “mark” duration is
determined by the device that generates the shortest “marks,” and
the “space” duration is determined by the device that generates the
longest “spaces.” Figure 14 shows the synchronization procedure.
A slave may stretch the space duration to slow down the bus
master. The space duration may also be stretched for handshaking
purposes. This can be done after each bit or after a complete byte
transfer. SIO1 will stretch the SCL space duration after a byte has
been transmitted or received and the acknowledge bit has been
transferred. The serial interrupt flag (SI) is set, and the stretching
continues until the serial interrupt flag is cleared.
SERIAL CLOCK GENERATOR
This programmable clock pulse generator provides the SCL clock
pulses when SIO1 is in the master transmitter or master receiver
mode. It is switched off when SIO1 is in a slave mode. The
programmable output clock frequencies are: f_OSC/120, f_OSC/9600,
and the Timer 1 overflow rate divided by eight. The output clock
1996 Aug 06
14