83C552 Datasheet, PDF (14/24 Pages) NXP Semiconductors – Single-chip 8-bit microcontroller

Philips Semiconductors
Single-chip 8-bit microcontroller
Product specification
80C552/83C552
AC ELECTRICAL CHARACTERISTICS (Continued)^{1, 2}
24/30 MHz version
24MHz CLOCK 30MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX MIN MAX
MIN
MAX
1/t_CLCL
2
t_LHLL
2
t_AVLL
2
t_LLAX
2
t_LLIV
2
t_LLPL
2
t_PLPH
2
t_PLIV
2
t_PXIX
2
t_PXIZ
2
t_AVIV
2
t_PLAZ
2
Data Memory
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
43
27
17
8
17
8
102
17
8
80
55
65
0
0
17
128
10
3.5
24
2t_CLCL–40
t_CLCL–25
t_CLCL–25
68
4t_CLCL–65
t_CLCL–25
3t_CLCL–45
40
3t_CLCL–60
0
8
t_CLCL–25
87
5t_CLCL–80
10
10
t_RLRH
3
RD pulse width
150
100
6t_CLCL–100
t_WLWH
4
WR pulse width
150
100
6t_CLCL–100
t_RLDV
3
RD low to valid data in
118
77
t_RHDX
3
Data hold after RD
0
0
0
t_RHDZ
3
Data float after RD
55
39
t_LLDV
3
ALE low to valid data in
183
117
t_AVDV
3
Address to valid data in
210
135
t_LLWL
3, 4 ALE low to RD or WR low
75
175
50
150
3t_CLCL–50
t_AVWL
3, 4 Address valid to WR low or RD low
92
58
4t_CLCL–75
t_QVWX
4
Data valid to WR transition
12
3
t_CLCL–30
t_DW
4
Data before WR
162
103
7t_CLCL–130
t_WHQX
4
Data hold after WR
17
8
t_CLCL–25
t_RLAZ
3
RD low to address float
0
0
t_WHLH
3, 4 RD or WR high to ALE high
17
67
8
58
t_CLCL–25
External Clock
t_CHCX
5
High time³
17
15
17
t_CLCX
5
Low time³
17
15
17
t_CLCH
5
Rise time³
5
3
t_CHCL
5
Fall time³
5
3
Serial Timing – Shift Register Mode³ (Test Conditions: T_amb = 0°C to +70°C; V_SS = 0V; Load Capacitance = 80pF)
t_XLXL
6
Serial port clock cycle time
0.5
0.4
12t_CLCL
t_QVXH
6
Output data setup to clock rising edge 283
200
10t_CLCL–133
t_XHQX
6
Output data hold after clock rising edge 23
6.6
2t_CLCL–60
t_XHDX
6
Input data hold after clock rising edge
0
0
0
t_XHDV
6
Clock rising edge to input data valid
283
200
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.
4. t_CLCL = 1/f_OSC = one oscillator clock period.
t_CLCL = 41.7ns at f_OSC = 24MHz.
5t_CLCL–90
2t_CLCL–28
8t_CLCL–150
9t_CLCL–165
3t_CLCL+50
0
t_CLCL+25
20
20
10t_CLCL–133
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
1998 Aug 13
14