74HC191 Datasheet, PDF (14/14 Pages) NXP Semiconductors – Presettable synchronous 4-bit binary up/down counter

Philips Semiconductors
Presettable synchronous 4-bit binary
up/down counter
Product specification
74HC/HCT191
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.16 Waveforms showing the set-up and hold times from the parallel load input (PL) to the data input (D_n).
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT : V_M = 1.3 V; V_I = GND to 3 V.
Fig.17 Waveforms showing the set-up and hold times from the count enable and up/down inputs (CE, U/D) to the
clock (CP).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
14