SAA5252 Datasheet, PDF (13/20 Pages) NXP Semiconductors – Line twenty-one acquisition and display LITOD

Philips Semiconductors
Line twenty-one acquisition and display (LITOD)
Product specification
SAA5252
I²C INTERFACE
Description of WRITE registers
The write subaddresses auto increment from 0 through to 4 at which point they stay until a new write subaddress is sent.
Registers are set to all logic 0 at power-up.
Table 3 Register 0 WRITE (Control Byte 1)
BIT
D0 to D3
D4
D5
D6
D7
DESCRIPTION
H0 to H3 set the offset position from the start of the horizontal sync pulse, set to a nominal value on reset.
Vertical sync pulse expected to be negative going logic 0 or positive-going logic 1.
Horizontal sync pulse expected to be negative going logic 0 or positive-going logic 1.
Video outputs will be positive going logic 0 or negative-going logic 1.
Data field select. When set to logic 0 Field 1 is decoded, when set to logic 1 Field 2 is decoded.
Table 4 Register 1 WRITE (Control Byte 2)
BIT
D0, D1
D2, D3
D4
D5
D6
D7
DESCRIPTION
Display mode selection bits. Table 8 shows the possible display modes.
Enhanced caption mode selection bits. Table 9 shows the possible enhanced caption modes.
When set to logic 1 acquisition of caption data is inhibited to allow the display to be used for
On-Screen Display purposes.
Acquisition window selection. When set to logic 0 only Line 21 is checked for caption data. When set to
logic 1, lines 19 to 23 of both fields are checked, allowing encrypted video signals to be handled.
User channel selection.
Clears the page memory when set HIGH. The page memory will be within two fields (30 ms).
Table 5 Register 2 WRITE (On-Screen Display data row address)
BIT
D0 to D3
DESCRIPTION
Row 0 to 3 sets the row address for On-Screen Display. This stored value will be incremented by overflow
increments of Register 3.
Table 6 Register 3 WRITE (On-Screen Display data column address)
BIT
D0 to D4
DESCRIPTION
Columns 0 to 4 sets the column address for On-Screen Display. This stored value will be incremented by
writes to Register 4.
Table 7 Register 4 WRITE (On-Screen Display data)
BIT
D0 to D6
DESCRIPTION
OSD0 to OSD6, On-Screen Display data bits writing to this register causes Register 3 to increment its
stored value.
1996 Jul 18
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