74HC137 Datasheet, PDF (13/19 Pages) NXP Semiconductors – 3-to-8 line decoder/demultiplexer with address latches; inverting

Philips Semiconductors
74HC137
3-to-8 line decoder, demultiplexer with address latches; inverting
PULSE
V_I
GENERATOR
V_CC
V_O
D.U.T.
R_T
C_L
mna101
Fig 9.
Test data is given in Table 9.
Definitions for test circuit:
R_T = Termination resistance should be equal to output impedance Z_o of the pulse generator.
C_L = Load capacitance including jig and probe capacitance.
Load circuitry for switching times
Table 9:
Supply
V_CC
2.0 V
4.5 V
6.0 V
5.0 V
Test data
Input
V_I
V_CC
V_CC
V_CC
V_CC
t_r, t_f
6 ns
6 ns
6 ns
6 ns
Load
C_L
50 pF
50 pF
50 pF
15 pF
13. Application information
strobe
decoder enable
X0
X1
X2
input
address
LE
A2 A1 A0
E1 E2
137
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
01234567
to five
X3
X4
other
decoders
X5
LE
A2 A1 A0
E1 E2
137
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
01234567
outputs
LE
A2 A1 A0
E1 E2
137
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
8 9 10 11 12 13 14 15
outputs
Fig 10. 6-to-64 line decoder with input address storage
LE
A2 A1 A0
E1 E2
137
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
16 17 18 19 20 21 22 23
outputs
001aab885
9397 750 13804
Product data sheet
Rev. 03 — 11 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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