SAA7114 Datasheet, PDF (121/147 Pages) NXP Semiconductors – PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI data slicer and high performance scaler

Philips Semiconductors
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI data slicer and high performance scaler
Product specification
SAA7114
Table 93 I port I/O enable, output clock and gated clock phase control; global set 87H[7:4]; note 1
OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL
ICLK default output phase
ICLK phase shifted by ¹â„₂ clock cycle ⇒ recommended for ICKS1 = 1
and ICKS0 = 0 (subaddress 80H)
ICLK phase shifted by approximately 3 ns
ICLK phase shifted by ¹â„₂ clock cycle + approximately
3 ns ⇒ alternatively to setting ‘01’
IDQ = gated clock default output phase
IDQ = gated clock phase shifted by ¹â„₂ clock cycle ⇒ recommended
for gated clock output
IDQ = gated clock phase shifted by approximately 3 ns
IDQ = gated clock phase shifted by ¹â„₂ clock cycle + approximately
3 ns ⇒ alternatively to setting ‘01’
CONTROL BITS D7 TO D4
IPCK3⁽²⁾ IPCK2⁽²⁾ IPCK1 IPCK0
X
X
0
0
X
X
0
1
X
X
1
0
X
X
1
1
0
0
X
X
0
1
X
X
1
0
X
X
1
1
X
X
Notes
1. X = don’t care.
2. IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1).
Table 94 I port I/O enable, output clock and gated clock phase control; global set 87H[1:0]
I PORT I/O ENABLE
I port output is disabled by software
I port output is enabled by software
I port output is enabled by pin ITRI at logic 0
I port output is enabled by pin ITRI at logic 1
CONTROL BITS D1 AND D0
IPE1
0
0
1
1
IPE0
0
1
0
1
2004 Mar 03
121