UDA1334BTS_15 Datasheet, PDF (12/22 Pages) NXP Semiconductors – Low power audio DAC

NXP Semiconductors
Low power audio DAC
Product specification
UDA1334BTS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I_DDD
digital supply current
normal operating mode
at 2.0 V supply voltage −
1.4
−
mA
at 3.0 V supply voltage −
2.1
−
mA
Sleep mode;
at 2.0 V supply voltage
clock running
−
250
−
μA
no clock running
−
20
−
μA
Sleep mode;
at 3.0 V supply voltage
clock running
−
375
−
μA
no clock running
−
30
−
μA
Digital input pins; note 2
V_IH
HIGH-level input voltage at 2.0 V supply voltage 1.3
−
at 3.0 V supply voltage 2.0
−
3.3
V
5.0
V
V_IL
LOW-level input voltage at 2.0 V supply voltage −0.5
−
at 3.0 V supply voltage −0.5
−
+0.5
V
+0.8
V
⎪I_LI⎪
input leakage current
C_i
input capacitance
−
−
1
μA
−
−
10
pF
3-level input: pin PCS
V_IH
HIGH-level input voltage
V_IM
MID-level input voltage
V_IL
LOW-level input voltage
0.9V_DDD
−
0.4V_DDD
−
−0.5
−
V_DDD + 0.5 V
0.6V_DDD
V
+0.5
V
DAC
V_ref(DAC)
R_o(ref)
I_o(max)
reference voltage
output resistance on
pin V_ref(DAC)
maximum output current
R_L
load resistance
C_L
load capacitance
with respect to V_SSA
(THD + N)/S < 0.1%;
R_L = 800 Ω
note 3
0.45V_DDA
−
0.5V_DDA
25
−
1.6
3
−
−
−
0.55V_DDA V
−
kΩ
−
mA
−
kΩ
50
pF
Notes
1. All supply connections must be made to the same external power supply unit.
2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be
accepted, but levels from 3.3 V domain can be applied to the pins.
3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.
2000 Jul 31
12