SAA7207H Datasheet, PDF (12/20 Pages) NXP Semiconductors – Reed Solomon decoder IC

Philips Semiconductors
Reed Solomon decoder IC
Product specification
SAA7207H
CHARACTERISTICS
V_DD = 5 V; T_amb = 25 °C; see notes 1 and 2; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital inputs: pins 35, 36 and 34 (DATA1, DATA0 and VALI); see Fig.7
V_IL
V_IH
t_r
t_f
t_SU;DAT
t_HD;DAT
C_Ii
LOW level input voltage
HIGH level input voltage
rise time
fall time
set-up time
hold time
input capacitance
−
−
2.0
−
−
−
−
−
7
−
5
−
−
5
0.8
V
−
V
5
ns
5
ns
−
ns
−
ns
−
pF
Digital outputs: pins 11 to 13, 15 to 17, 19, 20, 24 and 23 (BYTEO0 to BYTEO7, BEGIN and BERR); see Fig.8
V_OL
V_OH
t_d
t_HD;DAT
C_L
LOW level output voltage
HIGH level output voltage
delay time
hold time
load capacitance
C_L = 30 pF
C_L = 30 pF
0
−
0.9V_DD
−
2T_CLK − 30 −
2T_CLK − 30 −
−
−
0.1V_DD
V
V_DD
V
−
ns
−
ns
30
pF
Clock input: pin 38 (CLK)
t_CLK
cycle time
t_w
pulse width
t_r
rise time
t_f
fall time
−
31.5
−
ns
40 : 60 duty
12
−
19
ns
−
−
5
ns
−
−
5
ns
Clock output: pin 9 (BCLK)
t_BCLK
t_ow(BCLK)
BCLK cycle time
BCLK pulse width
4T_CLK
−
2T_CLK − 15 −
−
ns
2T_CLK + 15 ns
Notes
1. Detailed timing of the RESET, NOSYNC, Port 0 to Port 5 and test pins is assumed not to be relevant for the
application.
2. For a proper RESET procedure the RESET pin should be HIGH during at least 5 rising edges of the CLK pin.
1996 Jul 17
12