SAA4951 Datasheet, PDF (12/25 Pages) NXP Semiconductors – Memory controller

Philips Semiconductors
Memory controller
Preliminary specification
SAA4951
REGISTER BIT
MODE1 0 (LSB)
1
2
3
4
5
6
7
NAME
DR
STPWM1
STPWM2
MC1
GSC
CCIR60
EXTLLA
VFS
REMARKS
display raster
stop writing to memory 1: still picture mode
stop writing to memory 2: still picture mode
memory configuration bit 1
0: two field memories; 1: one field memory
golden scart
0: normal IPQ mode; 1: golden scart input
for external mode (13.5 MHz input clock) only:
0 = 50 Hz, 864 clock cycles per line; 1 = 60 Hz, 858 clock cycles per line
horizontal reference pulse BLNA and clock LLA from external source
0: internal (PLL); 1: external
vertical frequency select
VFS
DR
display mode
0
0
100 Hz (312.5 lines) ABAB raster
0
1
100 Hz (313/312.5/312/312.5 lines) AABB raster
1
0
50 Hz (625 lines) 1:1, non-interlaced
1
1
50 Hz (1250 lines) 2:1, interlaced
Description of acquisition part
LLA
This is the main input clock pulse for the acquisition side of
the memory controller generated by an external PLL
circuit. Depending on the chosen system application LLA
runs on the different frequencies of 12/13.5/16/18 MHz.
The PLL circuit is controlled by the analog burst key pulse
ABK provided by an inserted synchronization circuit (i. e.
TDA2579) and the horizontal reference signal HRA
supplied by the SAA4951 circuit.
WEXT
External write enable input for digital colour decoder
applications, where the write enable signal is generated by
the digital colour decoder. This signal is simply sampled by
LLA and fed out at WE1.
SWC1
The acquisition clock input signal LLA is connected
through the memory controller circuit. LLA is internally
buffered and put out as serial write clock SWC1 for the
memory 1. Additionally SWC1 is used as a clock signal for
the three AD-converters and for the formatter function.
ALDUV/VB
The output signal ALDUV (analog load for the
chrominance signals U and V) controls the formation of the
8-bit digital data information of the chrominance signals U
and V.
April 1994
12