PCF85102C-2 Datasheet, PDF (12/20 Pages) NXP Semiconductors – 256 x 8-bit CMOS EEPROMs with I2C-bus interface

Philips Semiconductors
256 × 8-bit CMOS EEPROMs with
I²C-bus interface
Product specification
PCF85102C-2; PCF85103C-2
11 I²C-BUS CHARACTERISTICS
All timing values are valid within the operating supply voltage and ambient temperature range and refer to V_IL and V_IH
with an input voltage swing from V_SS to V_DD; see Fig.10; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
f_SCL
clock frequency
0
100
kHz
t_BUF
bus free time between a STOP and START
condition
4.7
−
µs
t_HD;STA
START condition hold time after which first clock
pulse is generated
4.0
−
µs
t_LOW
LOW-level clock period
4.7
−
µs
t_HIGH
HIGH-level clock period
4.0
−
µs
t_SU;STA
set-up time for START condition
repeated start 4.7
−
µs
t_HD;DAT
data hold time
for bus compatible masters
5
−
µs
for bus devices
note 1
0
−
ns
t_SU;DAT
data set-up time
250
−
ns
t_r
SDA and SCL rise time
−
1
µs
t_f
SDA and SCL fall time
−
300
ns
t_SU;STO
set-up time for STOP condition
4.0
−
µs
Note
1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be
internally provided by a transmitter.
12 WRITE CYCLE LIMITS
Selection of the chip address is achieved by connecting the A0, A1 and A2 inputs to either V_SS or V_DD.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
E/W cycle timing
t_E/W
E/W cycle time
Endurance
N_E/W
E/W cycle per byte
internal oscillator
T_amb = −40 to +85 °C
T_amb = 22 °C
−
7
−
100000 −
−
−
1000000 −
UNIT
ms
cycles
cycles
2000 Feb 15
12