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83C652 Datasheet, PDF (12/22 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontrollers | |||
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Phlips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C652/83C652
AC ELECTRICAL CHARACTERISTICS1, 2 (16 MHz type)
16MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX
MIN
MAX
1/tCLCL
2
tLHLL
2
tAVLL
2
tLLAX
2
tLLIV
2
tLLPL
2
tPLPH
2
tPLIV
2
tPXIX
2
tPXIZ
2
tAVIV
2
tPLAZ
2
Data Memory
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
3.5
16
85
2tCLCLâ40
8
tCLCLâ55
28
tCLCLâ35
150
4tCLCLâ100
23
tCLCLâ40
143
3tCLCLâ45
83
3tCLCLâ105
0
0
38
tCLCLâ25
208
5tCLCLâ105
10
10
tRLRH
3, 4
RD pulse width
275
6tCLCLâ100
tWLWH
3, 4
WR pulse width
275
6tCLCLâ100
tRLDV
3, 4
RD low to valid data in
148
tRHDX
3, 4
Data hold after RD
0
0
tRHDZ
3, 4
Data float after RD
55
tLLDV
3, 4
ALE low to valid data in
350
tAVDV
3, 4
Address to valid data in
398
tLLWL
3, 4
ALE low to RD or WR low
138
238
3tCLCLâ50
tAVWL
3, 4
Address valid to WR low or RD low
120
4tCLCLâ130
tQVWX
3, 4
Data valid to WR transition
3
tCLCLâ60
tDW
3, 4
Data setup time before WR
288
7tCLCLâ150
tWHQX
3, 4
Data hold after WR
13
tCLCLâ50
tRLAZ
3, 4
RD low to address float
0
tWHLH
3, 4
RD or WR high to ALE high
23
103
tCLCLâ40
Shift Register
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
5
Serial port clock cycle time3
5
Output data setup to clock rising edge3
5
Output data hold after clock rising edge3
5
Input data hold after clock rising edge3
5
Clock rising edge to input data valid3
0.75
492
80
0
12tCLCL
10tCLCLâ133
2tCLCLâ117
0
492
External Clock
tCHCX
tCLCX
tCLCH
tCHCL
6
High time3
6
Low time3
6
Rise time3
6
Fall time3
20
20
20
20
20
20
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.
5tCLCLâ165
2tCLCLâ70
8tCLCLâ150
9tCLCLâ165
3tCLCL+50
0
tCLCL+40
10tCLCLâ133
tCLCL â tCLCX
tCLCL â tCHCX
20
20
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
1997 Dec 05
12
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