TDA8768A Datasheet, PDF (11/32 Pages) NXP Semiconductors – 12-bit, 70 Msps Analog-to-Digital Converter (ADC)

Philips Semiconductors
TDA8768A
12-bit, 70 Msps Analog-to-Digital Converter (ADC)
Table 6: Characteristics…continued
V_CCA = V₂ to V₄₄, V₃ to V₄ and V₄₁ to V₄₀ = 4.75 to 5.25 V; V_CCD = V₃₇ to V₃₈ and V₁₅ to V₁₇ = 4.75 to 5.25 V;
V_CCO = V₃₃ to V₃₄ = 3.0 to 3.6 V; AGND and DGND shorted together; T_amb = −40 to 85 °C; V_I(p-p) − V_I(p-p) = 1.9 V;
V_ref = V_CCA3−1.75 V; V_I(CM) = V_CCA3−1.6V; typical values measured at V_CCA = V_CCD = 5 V and V_CCO = 3.3 V, T_amb = 25 °C
and C_L = 10 pF; unless otherwise specified.
Symbol
Parameter
Conditions
Test ^[1] Min Typ
Max Unit
3-state output delay times; see Figure 4
t_dZH
enable HIGH
t_dZL
enable LOW
t_dHZ
disable HIGH
t_dLZ
disable LOW
C
-
5.1
C
-
7.0
C
-
9.7
C
-
9.5
9.0 ns
11 ns
14 ns
13 ns
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100% industrially tested.
[2] The circuit has two clock inputs: CLK and CLK. There are 5 modes of operation:
a) PECL mode 1: (DC level vary 1:1 with V_CCD) CLK and CLK inputs are at differential PECL levels.
b) PECL mode 2: (DC level vary 1:1 with V_CCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC level vary 1:1 with V_CCD) CLK input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to
decouple the CLK or CLK input to DGND via a 100 nF capacitor.
e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.
In that case CLK pin has to be connected to the ground.
[3] The ADC input range can be adjusted with an external reference connected to V_ref pin. This voltage has to be referenced to V_CCA;
see Figure 12.
[4] The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[5] Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics:
THD = 20 log ⁽----²----ⁿ----^d----⁾---²-----⁺-------⁽---³----^r---^d-----⁾---²----⁺-------⁽---⁴-_F---^t--₂^h-----⁾--²-----⁺------⁽----⁵----^t--^h-----⁾--²-----⁺------⁽---⁶-----^t--^h----⁾---²-
where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6.
[6] Signal-to-noise ratio (SNR) takes into account all harmonics above five and noise up to nyquist frequency; see Figure 8.
[7] Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up
to half of the clock frequency (Nyquist frequency). Conversion to SINAD is given by SINAD = ENOB × 6.02 + 1.76 dB; see Figure 5.
[8] Intermodulation measured relative to either tone with analog input frequencies of 20 and 20.1 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB below full scale for each input signal).
d3_(IM3) is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product.
[9] Output data acquisition: the output data is available after the maximum delay of t_d; see Figure 3.
9397 750 09656
Product data
Rev. 02 — 03 July 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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