TDA4886 Datasheet, PDF (11/52 Pages) NXP Semiconductors – 140 MHz video controller with I2C-bus

Philips Semiconductors
140 MHz video controller with I²C-bus
Product specification
TDA4886
10 CHARACTERISTICS
All voltages and currents are measured in a dedicated test circuit which is optimized for best high frequency
performance; all voltages are measured with respect to GND (pins 9 and 14); V_P = V_{P1, 2, 3} = 8 V (pins 7, 21,
18 and 15); T_amb = 25 °C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; nominal colour signals at signal
outputs (pins 22, 19 and 16); reference black level (V_rbl) approximately 0.77 V; nominal settings for brightness and
contrast; maximum settings for OSD contrast and gain; no subcontrast, modulation of contrast or limiting (V₂₄ ≥ 5 V); no
OSD fast blanking (pin 1 connected to ground); notes 1 to 3; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supplies
V_P
I_P
V_P1,2,3
I_P1,2,3
V_PSO
supply voltage (pin 7)
7.6
8.0 8.8
V
supply current (pin 7)
note 4
−
21 25
mA
channel supply voltage
(pins 21, 18 and 15)
7.6
8.0 8.8
V
channel supply current
signal outputs (pins 22,
−
(pins 21, 18 and 15)
19 and 16) open-circuit;
V_rbl ≈ 0.77 V; notes 4 and 5
supply voltage for signal switch signal outputs switched to
−
off (threshold at pin 7)
switch-off voltage
21 25
mA
−
7.2
V
Input clamping and vertical blanking input, validation of buffered I²C-bus data (pin 5)
V₅
input clamping and vertical
notes 6 and 7
blanking input signal
no vertical blanking,
−0.1 −
+1.2
no input clamping
vertical blanking,
no input clamping
1.6
−
2.6
input clamping,
no vertical blanking
3.5
−
V_P
I₅
input current
V₅ = 1 V
pin 5 connected to ground;
note 8
−
−0.2 −
−80 −60 −30
V₅ = −0.1 V; note 8
−250 −200 −100
t_r/f5
rise/fall time for input clamping note 6; see Fig.7
pulse, disable for vertical
−
−
75
blanking
t_W5
t_W5I2C
t_I2Cvalid
t_I2Cdead
width of input clamping pulse
0.6
−
−
width of vertical blanking pulse leading and trailing edge
10
for validation of buffered
I²C-bus data
threshold V₅ = 1.4 V; note 7
−
−
delay between leading edge of I²C-bus transmission in
−
vertical blanking pulse and
buffered mode completed;
validation of buffered I²C-bus leading edge threshold
−
2
data
dead time of I²C-bus receiver
after synchronizing vertical
blanking pulse in case of a
completed I²C-bus
V₅ = 1.4 V; note 7
leading edge threshold
V₅ = 1.4 V; note 7
15
−
−
transmission in buffered mode
V
V
V
µA
µA
µA
ns/V
µs
µs
µs
µs
1998 Nov 11
11