SC16C554 Datasheet, PDF (11/55 Pages) NXP Semiconductors – Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Table 2:
Symbol
IOW
Pin description…continued
Pin
Type
PLCC68 LQFP64 LQFP80
18
9
31
I
IRQ
15
-
-
O
n.c.
21, 49, -
52, 54,
55, 65
RESET
37
27
(RESET)
1, 10, -
20, 21,
30, 40,
41, 49,
52, 60,
61, 71,
80
53
I
RIA, RIB,
RIC, RID
8, 28, 63, 19, 18, 43, I
42, 62 30, 50 58, 3
RTSA, RTSB, 14, 22, 5, 13, 26, 35, O
RTSC, RTSD 48, 56 36, 44 66, 75
R/W
18
-
-
I
Description
Input/Output Write strobe (Active-LOW). This function is
associated with the 16 mode only. A logic 0 transition on this pin will
transfer the contents of the data bus (D0-D7) from the external CPU
to an internal register that is defined by address bits A0-A2. When
the 68 mode is selected, this pin functions as R/W (see definition
under R/W).
Interrupt Request or Interrupt ‘A’. This function is associated with
the 68 mode only. In the 68 mode, interrupts from UART channels
A-D are wire-ORed internally to function as a single IRQ interrupt.
This pin transitions to a logic 0 (if enabled by the interrupt enable
register) whenever a UART channel(s) requires service. Individual
channel interrupt status can be determined by addressing each
channel through its associated internal register, using CS and A3-A4.
In the 68 mode, and external pull-up resistor must be connected
between this pin and V_CC. The function of this pin changes to INTA
when operating in the 16 mode (see definition under INTA).
Not connected.
Reset. In the 16 mode, a logic 1 on this pin will reset the internal
registers and all the outputs. The UART transmitter output and the
receiver input will be disabled during reset time. (See Section 7.11
“SC16C554/554D external reset conditions” for initialization details.)
When 16/68 is a logic 0 (68 mode), this pin functions similarly, but as
an inverted reset interface signal, RESET.
Ring Indicator (Active-LOW). These inputs are associated with
individual UART channels, A through D. A logic 0 on this pin indicates
the modem has received a ringing signal from the telephone line. A
logic 1 transition on this input pin will generate an interrupt.
Request to Send (Active-LOW). These outputs are associated with
individual UART channels, A through D. A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send. Writing
a logic 1 in the modem control register MCR[1] will set this pin to a
logic 0, indicating data is available. After a reset this pin will be set to
a logic 1. This pin only affects the transmit and receive operations
when Auto RTS function is enabled via the Enhanced Feature
Register (EFR[6]) for hardware flow control operation.
Read/Write strobe. This function is associated with the 68 mode
only. This pin provides the combined functions for Read or Write
strobes.
Logic 1 = Read from UART register selected by CS and A0-A4.
Logic 0 = Write to UART register selected by CS and A0-A4.
9397 750 13132
Product data
Rev. 05 — 10 May 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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