PCD3359A Datasheet, PDF(11/32 Page) NXP Semiconductors – 8-bit microcontroller with DTMF generator and 128 bytes EEPROM

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PCD3359A Datasheet, PDF (11/32 Pages) NXP Semiconductors – 8-bit microcontroller with DTMF generator and 128 bytes EEPROM

◁

Philips Semiconductors

8-bit microcontroller with DTMF

generator and 128 bytes EEPROM

Product speciï¬cation

PCD3359A

6.6 Musical scale frequencies

Finally, two octaves of musical scale in steps of semitones

can be realized, again assuming an oscillator frequency

fxtal = 3.58 MHz (Table 10). It is suggested to define the

frequency by the HGF register while the LGF contains

00H, disabling Low Group Frequency generation.

Table 10 Musical scale frequencies and their

implementation

NOTE

D#5

F#5

G#5

A#5

C#6

D#6

F#6

G#6

A#6

C#7

D#7

HGF

VALUE

(HEX)

FREQUENCY (Hz)

STANDARD(1) GENERATED

622.3

659.3

698.5

740.0

784.0

830.6

880.0

923.3

987.8

1 046.5

1 108.7

1 174.7

1 244.5

1 318.5

1 396.9

1 480.0

1 568.0

1 661.2

1 760.0

1 864.7

1 975.5

2 093.0

2 217.5

2 349.3

2 489.0

622.5

659.5

697.9

741.1

782.1

832.3

879.3

931.9

985.0

1 044.5

1 111.7

1 179.0

1 245.1

1 318.9

1 402.1

1 482.2

1 572.0

1 655.7

1 768.5

1 875.1

1 970.0

2 103.3

2 223.3

2 358.1

2 470.4

Note

1. Standard scale based on A4 at 440 Hz.

7 EEPROM AND TIMER 2 ORGANIZATION

The PCD3359A has 128 bytes of Electrically Erasable

Programmable Read-Only Memory (EEPROM). Such

non-volatile storage provides data retention without the

need for battery backup. In telecom applications, the

EEPROM is used for storing redial numbers and for short

dialling of frequently used numbers. More generally,

EEPROM may be used for customizing microcontrollers,

such as to include a PIN code or a country code, to define

trimming parameters, to select application features from

the range stored in ROM.

The most significant difference between a RAM and an

EEPROM is that a bit in EEPROM, once written to a

logic 1, cannot be cleared by a subsequent write

operation. Successive write accesses actually perform a

logical OR with the previously stored information.

Therefore, to clear a bit, the whole byte must be erased

and re-written with the particular bit cleared. Thus, an

erase-and-write operation is the EEPROM equivalent of a

RAM write operation.

Whereas read access times to an EEPROM are

comparable to RAM access times, write and erase

accesses are much slower at 5 ms each. To make these

operations more efficient, several provisions are available.

First, the EEPROM array is structured into 32 four-byte

pages (see Fig.5) permitting access to 4 bytes in parallel

(write page, erase/write page and erase page). It is also

possible to erase and write individual bytes. Finally, the

EEPROM address register provides auto-incrementing,

allowing very efficient read and write accesses to

sequential bytes.

To simplify the erase and write timing, the derivative 8-bit

down-counter (Timer 2) with reload register is provided.

In addition to EEPROM timing, Timer 2 can be used for

general real-time tasks, such as for measuring signal

duration and for defining pulse widths.

1998 May 11

▷