BLM7G1822S-80AB_15 Datasheet, PDF (11/18 Pages) NXP Semiconductors – LDMOS 2-stage power MMIC

NXP Semiconductors
BLM7G1822S-80AB(G)
LDMOS 2-stage power MMIC

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T_case = 25 C; V_DS = 28 V;
I_Dq1 = 40 mA (carrier section, driver stage);
I_Dq2 = 90 mA (carrier section, final stage);
I_Dq1 = 20 mA (peaking section, driver stage);
V_GS = 0.9 V (peaking section, final stage).
Test signal: pulsed CW (t_p = 200 s;  = 10 %).
(1) f = 1805 MHz
(2) f = 1842.5 MHz
(3) f = 1880 MHz
Fig 9. Power gain and drain efficiency as function of
output power; typical values
T_case = 25 C; V_DS = 28 V;
I_Dq1 = 40 mA (carrier section, driver stage);
I_Dq2 = 90 mA (carrier section, final stage);
I_Dq1 = 20 mA (peaking section, driver stage);
V_GS = 0.9 V (peaking section, final stage).
Test signal: pulsed CW (t_p = 200 s;  = 10 %).
(1) f = 1805 MHz
(2) f = 1842.5 MHz
(3) f = 1880 MHz
Fig 10. Normalized phase response as a function of
output power; typical values

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T_case = 25 C; V_DS = 28 V; I_Dq1 = 40 mA (carrier section, driver stage); I_Dq2 = 90 mA (carrier section, final stage);
I_Dq1 = 20 mA (peaking section, driver stage); V_GS = 0.9 V (peaking section, final stage).
Test signal: 2-tone CW (f_c = 1842.5 MHz).
(1) IMD low
(2) IMD high
Fig 11. Intermodulation distortion as a function of tone spacing; typical values
BLM7G1822S-80AB_S-80ABG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 1 July 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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