74HC259 Datasheet, PDF (11/11 Pages) NXP Semiconductors – 8-bit addressable latch

Philips Semiconductors
8-bit addressable latch
Product specification
74HC/HCT259
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.9 Waveforms showing the conditional reset input (MR) to output (Q_n) propagation delays.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.11 Waveforms showing the address set-up and hold times for A_n inputs to LE input.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
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