74HC163 Datasheet, PDF (11/11 Pages) NXP Semiconductors – Presettable synchronous 4-bit binary counter; synchronous reset

Philips Semiconductors
Presettable synchronous 4-bit binary
counter; synchronous reset
Product specification
74HC/HCT163
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.11 Waveforms showing the MR set-up and hold times.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.12 Waveforms showing the CEP and CET set-up and hold times.
APPLICATION INFORMATION
The HC/HCT163 facilitate designing counters of any
modulus with minimal external logic.
The output is glitch-free due to the synchronous reset.
Fig.13 Modulo-5 counter.
December 1990
Fig.14 Modulo-11 counter.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
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