TZA3012AHW Datasheet, PDF (10/60 Pages) NXP Semiconductors – 30 Mbits/s up to 3.2 Gbits/s A-rateTM Fibre Optic Receiver

Philips Semiconductors
30 Mbits/s up to 3.2 Gbits/s
A-rate™ fibre optic receiver
Product specification
TZA3012AHW
Slice level adjustment
The TZA3012AHW uses a slice level circuit to counter the
affects of asymmetrical noise that can occur in some
optical transmission systems. The slice level circuit
improves pre-detection signal-to-noise ratio by adding a
DC offset to the input signal. The offset required will
depend on the characteristics of the photo detector in the
optical front-end and the amplitude of the received signal.
The slice level is adjustable between −50 mV and +50 mV
in 512 steps of 0.2 mV.
The slice level function is enabled by setting bits SL1
and SL2 in I²C-bus registers LIMLOS1CNF
(address BDH) and LIMLOS2CNF (address BFH) for
channel 1 and channel 2 respectively. The slice level is set
by sign and magnitude convention. The sign, either
positive or negative (polarity), is set by I²C-bus
bits SL1SGN and SL2SGN. The magnitude, 0 to 50 mV in
256 steps, is set by an 8-bit D/A converter via I²C-bus
register LIMSLICE1 (address C0H) and
LIMSLICE2 (C1H) for channel 1 and channel 2
respectively.
The introduced offset is not present at inputs IN and INQ
to prevent the logarithmic RSSI detector from detecting the
offset as a valid input signal.
Data and Clock Recovery (DCR)
The TZA3012AHW recovers the clock and data contents
from the incoming bit stream; see Fig.6. The DCR uses a
combined frequency and phase locking scheme, providing
reliable and quick data acquisition at any bit rate between
30 Mbits/s and 3.2 Gbits/s. The DCR contains a Voltage
Controlled Oscillator (VCO), Frequency Window Detector
(FWD), octave divider M, main divider N, fractional
divider K, reference divider R, and a phase detector.
The internal VCO is phase-locked to a reference clock
signal of typically 19.44 MHz applied to pins CREF and
CREFQ.
The FWD is a conventional frequency locked PLL, which,
at power-up, initially applies a coarse adjustment to the
free running VCO frequency. The FWD checks the VCO
frequency, which has to be within a 1000 ppm (parts per
million) window around the desired frequency. The FWD
then compares the divided VCO frequency (also available
on pins PRSCLO and PRSCLOQ) with the reference
frequency, usually 19.44 MHz, on pins CREF and
CREFQ. If the VCO frequency is found to be outside this
window, the FWD disables the Data Phase Detector
(DPD) and forces the VCO to a frequency within the
window. As soon as the ‘in window’ condition occurs,
which is visible on pin INWINDOW, the DPD starts
acquiring lock on the incoming bit stream. Since the VCO
frequency is very close to the expected bit rate, the phase
acquisition will be almost instantaneous, resulting in quick
phase lock to the incoming data stream.
Although the VCO is now locked to the incoming bit
stream, the FWD is still supervising the VCO frequency
and takes over control if the VCO drifts outside the
predefined frequency window. This might occur during a
‘loss of signal’ situation. Due to the FWD, the VCO
frequency is always close to the required bit rate, enabling
rapid phase acquisition if the lost input signal returns.
The default frequency window of 1000 ppm means that
the reference frequency does not need to be highly
accurate or stable. Any crystal-based oscillator that
generates a reasonably accurate frequency, such
as 100 ppm, is suitable.
2003 May 21
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