TDA8765 Datasheet, PDF (10/20 Pages) NXP Semiconductors – 10-bit high-speed Analog-to-Digital Converter ADC

Philips Semiconductors
10-bit high-speed Analog-to-Digital
Converter (ADC)
Preliminary specification
TDA8765
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Timing (C_L = 10 pF); see Fig.5 and note 7
t_d(s)
sampling delay time
t_h
output hold time
t_d
output delay time
V_CCO = 5.25 V
V_CCO = 3.0 V
−
−
2
ns
4
−
−
ns
−
10
15
ns
−
13
18
ns
3-state output delay times; see Fig.6
t_dZH
enable HIGH
t_dZL
enable LOW
t_dHZ
disable HIGH
t_dLZ
disable LOW
−
14
18
ns
−
16
20
ns
−
16
20
ns
−
14
18
ns
Notes
1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation:
a) PECL mode 1 (DC level varies equal to DC level of V_CCD): CLK and CLK inputs are at differential PECL levels.
b) PECL mode 2 (DC level varies equal to DC level of V_CCD): CLK input is at PECL level and sampling is taken on
the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.
c) PECL mode 3 (DC level varies equal to DC level of V_CCD): CLK input is at PECL level and sampling is taken on
the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a
100 nF capacitor.
d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with
a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.
2. It is possible with an external reference connected to pin V_ref to adjust the ADC input range. This voltage has to be
referenced to V_CCA. For V_CCA − 1.825 V, the differential input voltage amplitude is 2 V (p-p).
3. The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a
full-scale sine wave.
4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
THD = 20 log-------------------------------------------------------F--------------------------------------------------------
(2nd)2 + (3rd)2 + (4th)2 + (5th)2 + (6th)2
where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all
harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR:
SNR = N_bit × 6.02 + 1.76 dB.
6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB
below full scale for each input signal).
d₃ is the ratio of the RMS-value of either input tone to the RMS-value of the worst case third order intermodulation
product.
7. Output data acquisition: the output data is available after the maximum delay of t_d.
1999 Jan 06
10