TDA4850 Datasheet, PDF (10/20 Pages) NXP Semiconductors – Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors

Philips Semiconductors
Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors
Product specification
TDA4850
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Horizontal output (open-collector); see Fig.3
V₃
output voltage LOW
I₃ = 20 mA
I₃ = 60 mA
t_p/t_H
t_H duty cycle
V_P
threshold to activate too low supply voltage horizontal output off
protection
horizontal output on
Horizontal clamping/blanking generator output; see Fig.3
V₈
output voltage LOW
H and V scanning
blanking output voltage
internal V blanking
external H blanking
clamping output voltage
H-sync on pin 9
I₈
internal sink current for all output levels
H and V scanning
t₈
clamping pulse start
t_clp
clamping pulse width
S
steepness of rise and fall times
Vertical oscillator (V_ref = 6.25 V)
f_o
vertical free-running frequency
f_V
nominal vertical sync range
V₁₅
voltage on pin 15
t_d
delay between sync pulse and start of
vertical scan
in VGA/XGA mode, activated by an
external resistor on pin 7
in multi-frequency mode
I₁₂
control current for amplitude control
C₁₂
capacitor for amplitude control
R₁₅ = 22 kΩ;
C₁₆ = 0.1 µF
no f_o adjustment
R₁₅ = 22 kΩ
measured on pin 8
V₇ < 50 mV
Vertical differential output; see Fig.4
I_o
differential output current between
pins 5 and 6 (peak-to-peak value)
maximum offset current error
maximum linearity error
mode 3; I₁₃ > −135 µA;
R₁₅ = 22 kΩ
I_o = 1 mA
−
−
0.3
−
−
0.8
42
45
48
−
5.3
−
−
5.6
−
−
−
0.9
1.8 2.1 2.4
1.8 2.1 2.4
3.5 3.9 4.3
2.3 2.9 3.5
with end of H-sync
0.8 1.0 1.2
−
40
−
40
42
43.3
50
−
110
2.8 3.0 3.2
500 575 650
240 300 360
−
±200 −
−
−
0.33
0.9 1.0 1.1
−
−
±2.5
−
−
±1.5
V
V
%
V
V
V
V
V
V
mA
µs
ns/V
Hz
Hz
V
µs
µs
µA
µF
mA
%
%
1997 Jun 05
10