PCA9540BD Datasheet, PDF (10/14 Pages) NXP Semiconductors – 2-channel I2C multiplexer

Philips Semiconductors
2-channel I²C multiplexer
Product data sheet
PCA9540B
AC CHARACTERISTICS
SYMBOL
PARAMETER
t_pd
f_SCL
t_BUF
t_HD;STA
Propagation delay from SDA to SD_n or SCL to SC_n
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
STANDARD-MODE
I²C-BUS
MIN
MAX
—
0.3¹
0
100
4.7
—
4.0
—
FAST-MODE
I²C-BUS
MIN
MAX
—
0.3¹
0
400
1.3
—
0.6
—
UNIT
ns
kHz
µs
µs
t_LOW
LOW period of the SCL clock
4.7
—
1.3
—
µs
t_HIGH
HIGH period of the SCL clock
4.0
—
0.6
—
µs
t_SU;STA Set-up time for a repeated START condition
4.7
—
0.6
—
µs
t_SU;STO Set-up time for STOP condition
4.0
—
0.6
—
µs
t_HD;DAT Data hold time
0²
3.45
0²
0.9
µs
t_SU;DAT Data set-up time
250
—
100
—
ns
t_R
Rise time of both SDA and SCL signals
t_F
Fall time of both SDA and SCL signals
—
1000
20 + 0.1C_b3
300
ns
—
300
20 + 0.1C_b3
300
µs
C_b
Capacitive load for each bus line
—
400
—
400
µs
t_SP
Pulse width of spikes which must be suppressed
by the input filter
—
50
—
50
ns
t_VD:DATL Data valid (HL)⁴
—
1
—
1
µs
t_VD:DATH Data valid (LH)⁴
—
0.6
—
0.6
µs
t_VD:ACK Data valid Acknowledge
—
1
—
1
µs
NOTES:
1. Pass gate propagation delay is calculated from the 20 Ω typical R_ON and and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH_min of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. C_b = total capacitance of one bus line in pF.
4. Measurements taken with 1 kΩ pull-up resistor and 50 pF load.
SDA
t_BUF
t_LOW
t_R
t_F
SCL
P
t_HD;STA
S
t_HD;DAT
t_HIGH
t_SU;DAT
t_HD;STA
t_SU;STA
Sr
Figure 13. Definition of timing on the I²C-bus
t_SP
t_SU;STO
P
SU00645
2004 Sep 29
10