P90CE201 Datasheet, PDF (10/77 Pages) NXP Semiconductors – 16-bit microcontroller

Philips Semiconductors
16-bit microcontroller
Product specification
P90CE201
handbook, full pagewidth
BIT 15
13
10
8
4
0
T – S – – 12 11 10 – – – X N Z V C
Supervisor
Trace State
Mode
Interrupt
Mask
Carry
Overflow
Zero
Negative
Extend
MCD506
Fig.5 Status Register.
5.3 Internal and external operation
The P90CE201 operates with an internal clock frequency
of half the oscillator frequency (f_OSC/2). Each internal clock
cycle is divided into 2 states. A non-access machine cycle
has 3 clock cycles or 6 states (S0 to S5). A minimum bus
cycle normally consists of 3 clock cycles (6 states). When
data transfer has not yet been terminated, wait states (SW)
are inserted in multiples of 2. For external memory access,
2 wait states (bus states SB) are added automatically.
5.4 Processing states and exception processing
The CPU is always in one of three processing states:
normal, exception or halted.
The normal processing state is that associated with
instruction execution; the memory references are to fetch
instructions and operands and to store results. A special
case of the normal state is the stopped state which the
processor enters when a STOP instruction is executed. In
this state the CPU makes no further memory references.
The exception processing state is associated with
interrupts, trap instructions, tracing and other exceptional
conditions. The exception may be generated internally by
an instruction or by an unusual condition arising during the
execution of an instruction. Externally, exception
processing can be forced by an interrupt or a reset.
The halted processing state is an indication of a
catastrophic hardware failure. For example, if during
exception processing of a bus error another bus error
occurs, the CPU assumes that the system is unusable and
halts. Only an external reset can restart a halted
processor. Note that a CPU in the stopped state is not in
the halted state or vice versa.
The processor can work in the “user” or “supervisor” state
determined by the state of the S-bit in the Status Register.
Accesses to the on-chip peripherals are achieved in the
supervisor state.
All exception processing is performed in the supervisor
state once the current content of the Status Register has
been copied. The exception vector number is then
determined and copies of the Status Register, the
Program Counter value and the format/vector number are
saved on the supervisor stack using the Supervisor Stack
Pointer. Finally, the contents of the exception vector
location is fetched and loaded into the Program Counter.
August 1993
10