83C750 Datasheet, PDF (10/16 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 1K/64 OTP ROM, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
1K/64 OTP/ROM, low pin count
Product specification
83C750/87C750
Programming and Verifying Security Bits
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 3. When
programming either security bit, it is not necessary to provide
address or data information to the 87C750 on ports 1 and 3.
Verification occurs in a similar manner using the RESET serial
stream shown in Table 3. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if not programmed. Likewise, P1.6
contains the security bit 2 data and is a logical one if programmed
and a logical zero if not programmed.
Table 3. Implementing Program/Verify Modes
OPERATION
Program user EPROM
Verify user EPROM
Program key EPROM
Verify key EPROM
Program security bit 1
Program security bit 2
Verify security bits
NOTE:
1. Pulsed from V_IH to V_IL and returned to V_IH.
SERIAL CODE
296H
296H
292H
292H
29AH
298H
29AH
P0.1 (PGM/)
–¹
V_IH
–¹
V_IH
–¹
–¹
V_IH
EPROM PROGRAMMING AND VERIFICATION
T_amb = 21°C to +27°C, V_CC = 5V ±10%, V_SS = 0V
SYMBOL
PARAMETER
MIN
1/t_CLCL
t_AVGL1
Oscillator/clock frequency
Address setup to P0.1 (PROG–) low
1.2
10µs + 24t_CLCL
t_GHAX
Address hold after P0.1 (PROG–) high
48t_CLCL
t_DVGL
Data setup to P0.1 (PROG–) low
38t_CLCL
t_DVGL
Data setup to P0.1 (PROG–) low
38t_CLCL
t_GHDX
Data hold after P0.1 (PROG–) high
36t_CLCL
t_SHGL
V_PP setup to P0.1 (PROG–) low
10
t_GHSL
V_PP hold after P0.1 (PROG–)
10
t_GLGH
P0.1 (PROG–) width
90
t_AVQV2
V_PP low (V_CC) to data valid
t_GHGL
P0.1 (PROG–) high to P0.1 (PROG–) low
10
t_SYNL
P0.0 (sync pulse) low
4t_CLCL
t_SYNH
P0.0 (sync pulse) high
8t_CLCL
t_MASEL
ASEL high time
13t_CLCL
t_MAHLD
Address hold time
2t_CLCL
t_HASET
Address setup to ASEL
13t_CLCL
t_ADSTA
Low address to valid data
NOTES:
1. Address should be valid at least 24t_CLCL before the rising edge of P0.2 (V_PP).
2. For a pure verify mode, i.e., no program mode in between, t_AVQV is 14t_CLCL maximum.
MAX
6
110
48t_CLCL
48t_CLCL
P0.2 (V_PP)
V_PP
V_IH
V_PP
V_IH
V_PP
V_PP
V_IH
UNIT
MHz
µs
µs
µs
µs
1998 May 01
10