SSTUH32865 Datasheet, PDF (1/28 Pages) NXP Semiconductors – 1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applications

SSTUH32865
1.8 V 28-bit high output drive 1:2 registered buffer with parity
for DDR2 RDIMM applications
Rev. 01 — 11 March 2005
Product data sheet
1. General description
The SSTUH32865 is a 1.8 V 28-bit high output drive 1:2 register specifically designed for
use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2)
memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but
integrates the functionality of the normally required two registers in a single package,
thereby freeing up board real-estate and facilitating routing to accommodate high-density
Dual In-line Memory Module (DIMM) designs.
The SSTUH32865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
The SSTUH32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin profile
fine-pitch ball grid array (TFBGA) package, which—while requiring a minimum
9 mm × 13 mm of board space—allows for adequate signal routing and escape using
conventional card technology.
The SSTUH32865 is identical to SSTU32865 in function and performance, with
higher-drive outputs optimized to drive heavy load nets (such as stacked DRAMs) while
maintaining speed and signal integrity.
2. Features
s 28-bit data register supporting DDR2
s Higher output drive strength version of SSTU32865 optimized for high-capacitive load
nets
s Fully compliant to JEDEC standard JESD82-9
s Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2 × SSTU32864 or 2 × SSTU32866)
s Parity checking function across 22 input data bits
s Parity out signal
s Controlled output impedance drivers enable optimal signal integrity and speed
s Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation
delay, 2.0 ns max. mass-switching)
s Supports up to 450 MHz clock frequency of operation
s Optimized pinout for high-density DDR2 module design
s Chip-selects minimize power consumption by gating data outputs from changing state
s Supports Stub Series Terminated Logic SSTL_18 data inputs
s Differential clock (CK and CK) inputs