SCN26562 Datasheet, PDF (1/17 Pages) NXP Semiconductors – Dual universal serial communications controller DUSCC

Philips Semiconductors
Dual universal serial communications controller (DUSCC)
Product specification
SCN26562
DESCRIPTION
The Philips Semiconductors SCN26562 Dual Universal Serial
Communications Controller (DUSCC) is a single-chip MOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SCN26562 interfaces to synchronous
bus MPUs and is capable of program-polled, interrupt driven,
block-move or DMA data transfers.
The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multi-function counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides 16 common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock, making the
DUSCC well suited for dual-speed channel applications. Data rates
up to 4Mbits per second are supported.
The transmitter and receiver each contain a four-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to four characters at
a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
Two modem control inputs (DCD and CTS) and three modem
control outputs (RTS and two general purpose) are provided.
Because the modem control inputs and outputs are general purpose
in nature, they can be optionally programmed for other functions.
This document contains the electrical specifications for the
SCN26562. See SCN26562/SCN68562 User’s Guide for complete
functional description.
FEATURES
General Features
• Dual full-duplex synchronous/asynchronous receiver and
transmitter
• Multiprotocol operation
– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
– COP: BISYNC, DDCMP
– ASYNC: 5–8 bits plus optional parity
• Four character receiver and transmitter FIFOs
• 0 to 4Mbit/sec data rate
• Programmable bit rate for each receiver and transmitter selectable
from:
– 16 fixed rates: 50 to 38.4k baud
– One user-defined rate derived from programmable
counter/timer
– External 1X or 16X clock
– Digital phase-locked loop
• Parity and FCS (frame check sequence LRC or CRC) generation
and checking
• Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
• Programmable channel mode: full- and half-duplex, auto-echo, or
local loopback
• Programmable data transfer mode: polled, interrupt, DMA, wait
• DMA interface
– Single- or dual-address dual transfers
– Half- or full-duplex operation
– Automatic frame termination on counter/timer terminal count or
DMA EOPN input
• Interrupt capabilities
– Vector output (fixed or modified by status)
– Programmable internal priorities
– Maskable interrupt conditions
• Multi-function programmable 16-bit counter/timer
– Bit rate generator
– Event counter
– Count received or transmitted characters
– Delay generator
– Automatic bit length measurement
• Modem controls
– RTS, CTS, DCD, and up to four general purpose pins per
channel
– CTS and DCD programmable auto-enables for Tx and Rx
– Programmable interrupt on change of CTS or DCD
• On-chip oscillator for crystal
• TTL compatible
• Single +5V power supply
Asynchronous Mode Features
• Character length: 5 to 8 bits
• Odd or even parity, no parity, or force parity
• Up to two stop bits programmable in 1/16-bit increments
• 1X or 16X and Tx clock factors
• Parity, overrun, and framing error detection
• False start bit detection
• Start bit search 1/2-bit time after framing error detection
• Break generation with handshake for counting break characters
• Detection of start and end of received break
• Character compare with optional interrupt on match
• Transmits up to 4Mbit/sec data rate Receives up to 2Mbit/sec data
rate
1995 May 1
1
853-0307 15179