SC18IS600 Datasheet, PDF (1/28 Pages) NXP Semiconductors – SPI to IC-bus interface

SC18IS600/601
SPI to I²C-bus interface
Rev. 03 — 13 December 2006
Product data sheet
1. General description
The SC18IS600/601 is designed to serve as an interface between the standard SPI of a
host (microcontroller, microprocessor, chip set, etc.) and the serial I²C-bus. This allows
the host to communicate directly with other I²C-bus devices. The SC18IS600/601 can
operate as an I²C-bus master-transmitter or master-receiver. The SC18IS600/601
controls all the I²C-bus specific sequences, protocol, arbitration and timing.
The key distinction between the SC18IS600 and the SC18IS601 lies in the clock source:
internal (SC18IS600) versus external (SC18IS601).
2. Features
I SPI slave interface
I SPI Mode 3
I Master I²C-bus controller
I General Purpose Input/Output (GPIO) pins: 4 (SC18IS600); 3 (SC18IS601)
I Two quasi-bidirectional I/O pins
I 5 V tolerant I/O pins
I High-speed SPI:
N Up to 3 Mbit/s (SC18IS601)
N Up to 1.2 Mbit/s (SC18IS600)
I High-speed I²C-bus: 400 kbit/s
I 96-byte transmit buffer
I 96-byte receive buffer
I 2.4 V to 3.6 V operation
I Power-down mode with WAKEUP pin
I Oscillator: internal (SC18IS600); external (SC18IS601)
I Active LOW interrupt output
I Available in very small TSSOP16 package
3. Ordering information
Table 1. Ordering information
Type number Package
Name
Description
SC18IS600IPW TSSOP16 plastic thin shrink small outline package; 16 leads;
SC18IS601IPW
body width 4.4 mm
Version
SOT403-1