PLS100 Datasheet, PDF (1/8 Pages) NXP Semiconductors – Programmable logic arrays 16 × 48 × 8

Philips Semiconductors Programmable Logic Devices
Programmable logic arrays
(16 × 48 × 8)
Product specification
PLS100/PLS101
DESCRIPTION
The PLS100 (3-State) and PLS101 (Open
Collector) are bipolar, fuse Programmable
Logic Arrays (PLAs). Each device utilizes the
standard AND/OR/Invert architecture to
directly implement custom sum of product
equations.
Each device consists of 16 dedicated inputs
and 8 dedicated outputs. Each output is
capable of being actively controlled by any or
all of the 48 product terms. The True,
Complement, or Don’t Care condition of each
of the 16 inputs and be ANDed together to
comprise one P-term. All 48 P-terms can be
selectively ORed to each output.
The PLS100 and PLS101 are fully TTL
compatible, and chip enable control for
expansion of input variables and output
inhibit. They feature either Open Collector or
3-State outputs for ease of expansion of
product terms and application in
bus-organized systems.
Order codes are listed in the Ordering
Information Table.
FEATURES
• Field-programmable (Ni-Cr link)
• Input variables: 16
• Output functions: 8
• Product terms: 48
• I/O propagation delay: 50ns (max.)
• Power dissipation: 600mW (typ.)
• Input loading: –100µA (max.)
• Chip Enable input
• Output option:
– PLS100: 3-State
– PLS101: Open-Collector
• Output disable function:
– 3-State: Hi-Z
– Open-Collector: High
APPLICATIONS
• CRT display systems
• Code conversion
• Peripheral controllers
• Function generators
• Look-up and decision tables
• Microprogramming
• Address mapping
• Character generators
• Data security encoders
• Fault detectors
• Frequency synthesizers
• 16-bit to 8-bit bus interface
• Random logic replacement
PIN CONFIGURATIONS
N Package
FE* 1
I7 2
I6 3
I5 4
I4 5
I3 6
I2 7
I1 8
I0 9
F7 10
F6 11
F5 12
F4 13
GND 14
28 V_CC
27 I8
26 I9
25 I10
24 I11
23 I12
22 I13
21 I14
20 I15
19 CE
18 F0
17 F1
16 F2
15 F3
* Fuse Enable Pin: It is recommended that this pin
be left open or connected to ground during normal
operation.
N = Plastic DIP (600mil-wide)
A Package
I5 I6 I7 FE V_CC I8 I9
4 3 2 1 28 27 26
I4 5
25 I10
I3 6
24 I11
I2 7
23 I12
I1 8
22 _I13
I0 9
21 I14
F7 ¹⁰
20 I15
F6 11
19 CE
12 13 14 15 16 17 18
F5 F4 GND F3 F2 F1 F0
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
28-Pin Plastic Dual In-Line 600mil-wide
28-Pin Plastic Leaded Chip Carrier
3-STATE
PLS100N
PLS100A
OPEN COLLECTOR
PLS101N
PLS101A
DRAWING NUMBER
0413D
0401F
October 22, 1993
49
853–0308 11164