PHX2N40E Datasheet, PDF (1/5 Pages) NXP Semiconductors – PowerMOS transistor Isolated version of PHP4N40E

Philips Semiconductors
PowerMOS transistor
Isolated version of PHP4N40E
Objective specification
PHX2N40E
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a full
pack, plastic envelope featuring high
avalanche energy capability, stable
blocking voltage, fast switching and
high thermal cycling performance
with low thermal resistance. Intended
for use in Switched Mode Power
Supplies (SMPS), motor control
circuits and general purpose
switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
400
2.4
25
1.8
UNIT
V
A
W
Ω
PINNING - SOT186A
PIN
DESCRIPTION
1 gate
2 drain
3 source
case isolated
PIN CONFIGURATION
case
12 3
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
I_D
I_DM
I_DR
I_DRM
P_tot
T_stg
T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (pulse peak
value)
Source-drain diode current
(DC)
Source-drain diode current
(pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
R_GS = 20 kΩ
T_hs = 25 ˚C
T_hs = 100 ˚C
T_hs = 25 ˚C
T_hs = 25 ˚C
T_hs = 25 ˚C
T_hs = 25 ˚C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W_DSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
W_DSR1
Drain-source repetitive
unclamped inductive turn-off
energy
CONDITIONS
I_D = 4.2 A ; V_DD ≤ 50 V ; V_GS = 10 V ;
R_GS = 50 Ω
T_j = 25˚C prior to surge
T_j = 100˚C prior to surge
I_D = 4.2 A ; V_DD ≤ 50 V ;
V_GS = 10 V ; R_GS = 50 Ω ; T_j ≤ 150 ˚C
MIN.
-
-
-
-
-
-
-
-
-
-55
-
MIN.
-
-
-
MAX.
400
400
30
2.4
1.5
9.6
2.4
9.6
25
150
150
MAX.
190
35
5
UNIT
V
V
V
A
A
A
A
A
W
˚C
˚C
UNIT
mJ
mJ
mJ
1. Pulse width and frequency limited by T_j(max)
November 1996
1
Rev 1.000