PHP20N06E Datasheet, PDF (1/7 Pages) NXP Semiconductors – PowerMOS transistor

Philips Semiconductors
PowerMOS transistor
Product specification
PHP20N06E
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode
field-effect power transistor in a plastic
envelope.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding, DC/DC
and AC/DC converters, and in
automotive and general purpose
switching applications.
SYMBOL
V_DS
I_D
P_tot
T_j
R_DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
MAX.
60
22
75
175
0.08
UNIT
V
A
W
˚C
Ω
PINNING - TO220AB
PIN
DESCRIPTION
1 gate
2 drain
3 source
tab drain
PIN CONFIGURATION
tab
1 23
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
V_DS
Drain-source voltage
-
-
V_DGR
Drain-gate voltage
R_GS = 20 kΩ
-
±V_GS
Gate-source voltage
-
-
I_D
Drain current (DC)
T_mb = 25 ˚C
-
I_D
Drain current (DC)
T_mb = 100 ˚C
-
I_DM
Drain current (pulse peak value) T_mb = 25 ˚C
-
P_tot
Total power dissipation
T_mb = 25 ˚C
-
T_stg
Storage temperature
-
- 55
T_j
Junction temperature
-
-
THERMAL RESISTANCES
SYMBOL
R_{th j-mb}
R_{th j-a}
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
MAX.
60
60
30
22
15
88
75
175
175
UNIT
V
V
V
A
A
A
W
˚C
˚C
MIN. TYP. MAX. UNIT
-
-
2 K/W
-
60
- K/W
August 1996
1
Rev 1.000